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Pushing the barriers of wafer level device integration
Written by Gordon Christison   
Tuesday, 08 July 2008

Techsearch has predicted a compound annual growth rate of more than 24% for wafer-level packages between 2005 and 2010. Contract electronics manufacturers and original design manufacturers face a range of handling problems when using these small silicon devices in assemblies.

 
Are we there yet?
Written by Joe Fjelstad   
Tuesday, 08 July 2008

The ongoing journey to co-design of chip, package and substrate.

 
Process and assembly methods for increased yield of PoP devices
Written by Brian Toleno, Ph.D., and Dan Maslyk   
Wednesday, 02 July 2008
Increased functionality and smaller devices are significant drivers in innovative packaging designs.
 
Assessing the impact of contamination in an SMT production environment
Written by Sheila Hamilton, Technical Director, Teknek   
Wednesday, 25 June 2008
By Sheila Hamilton, Technical Director of TeknekPresenting the contamination analysis in this way makes it immediately obvious where housekeeping procedures or manufacturing protocols need to be increased or changed within the department.
 
Time for the electronics industry to clean up its act?
Written by Hunter Paterson, Product Manager, Teknek   
Tuesday, 24 June 2008
Research has shown that 80% of contaminants are introduced in to a “clean area” by people and products, 15% is generated by the products themselves and 5% is actually produced by the room and filtration system.
 
Ball grid array & lead-free assembly defects, part 1
Written by Bob Willis   
Monday, 16 June 2008

Over the last few years I have been asked to examine many different ball grid array (BGA) defects from assembly and on field failures here are a selection of the defects and some of the popular causes.

 
Wafer-level cavity package with via-through pad interconnects
Written by Giles Humpston   
Monday, 16 June 2008
The continued drive toward solid state imagers with greater pixel numbers and smaller pixels adversely affects yields, particularly through physical contamination during assembly of the camera module.
 
Tools & Methods for Lean Production Management in EA
Written by Dr. T. Nguyen & Vern Harrison   
Monday, 16 June 2008

Lean manufacturing is far from a new concept, and many within the electronics assembly (EA) industry are already familiar with the principles and concepts behind it.

 
Nanotechnology and mathematical methods for high-performance thermal interface materials
Written by Sara N. Paisner, PhD   
Monday, 16 June 2008
Higher power chips have resulted from a variety of new developments in the electronics industry.

 

 
Change in the electronics industry – slow but inevitable
Written by Joe Fjelstad   
Monday, 09 June 2008

Approaching four decades of working in the electronics interconnection industry, it appears to this observer that, when looking back over all those years, the electronics interconnection manufacturing industry has been on a treadmill of sorts and changing ever so slowly.

 
Improving print performance using area ratio sensitivity analysis
Written by Chris Anglin   
Monday, 09 June 2008
The purpose of a solder paste print evaluation is to observe variation in transfer efficiency to the assembly process under conditions that permit careful scrutiny.
 
Case Study: Technology partnership for effective RFID system solutions
Written by Dipl.-Ing. (FH) Florian Hierl   
Wednesday, 21 May 2008
The market for contactless labels has passed through the trough and out the other side—RFID is gaining momentum again: In 2007, 144 million RFID tags were sold in the EU alone.
 
Static control - Training is still the key to success
Written by Global SMT & Packaging   
Wednesday, 21 May 2008
The electronics industry is continually faced with problems that take time and money to solve. Many of the problems are by no means new. Possibly they may be areas that were not considered important.
 
"REACH for the sky…"
Written by Global SMT & Packaging   
Wednesday, 14 May 2008
Will the latest bit of environmental legislation be a hold up?
 
Challenges for high density PoP (package-on-package) utilizing SoP (solder-on-pad)
Written by Joanna Kristine Wildhart and Moody Dreiza   
Wednesday, 14 May 2008
This paper covers the surface mount and package stacking assembly challenges related to high density package-on-package (PoP) utilizing solder-on-pad (SOP) technology.
 
Thermal profiling optimizes printed circuit board assembly
Written by Etienne Witte and Paul Austen   
Wednesday, 07 May 2008
This article describes thermal profiling hardware and process management software solutions as used at EMS provider Axiom Electronics LLC to meet the thermal profiling challenges of today’s microelectronics environment.
 
Cleaning process integration of cleaning material with cleaning equipment
Written by Mike Bixenman and Steve Stach   
Wednesday, 30 April 2008

Innovative electronic assembly designs strive to increase functionality over smaller surface areas. Highly dense circuit assembly designs increase the cleaning challenge.

 
BGA & stack packages - making dummy parts
Written by Bob Willis   
Monday, 21 April 2008


Ball Grid Array BGAs are a widely used technology in a vast range of products, including consumer, telecommunications and office-based systems.

 
Reducing cost in the EMS supply chain through niche sourcing
Written by Dawn Poirier   
Wednesday, 16 April 2008

The EMS industry has created many business models, including those where OEMs provide value-added assembly services in addition to a proprietary product.

 
Process requirements for high density SMD placement
Written by Sjef van Gastel   
Wednesday, 09 April 2008

As the drive towards assembly miniaturization continues and surface mount technology matures, components are becoming ever smaller and thinner.

 
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