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Pushing the barriers of wafer level device integration
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Written by Gordon Christison   
Tuesday, 08 July 2008

Techsearch has predicted a compound annual growth rate of more than 24% for wafer-level packages between 2005 and 2010. Contract electronics manufacturers and original design manufacturers face a range of handling problems when using these small silicon devices in assemblies.

 
Process and assembly methods for increased yield of PoP devices
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Written by Brian Toleno, Ph.D., and Dan Maslyk   
Wednesday, 02 July 2008
Increased functionality and smaller devices are significant drivers in innovative packaging designs.
 
Assessing the impact of contamination in an SMT production environment
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Written by Sheila Hamilton, Technical Director, Teknek   
Wednesday, 25 June 2008
By Sheila Hamilton, Technical Director of TeknekPresenting the contamination analysis in this way makes it immediately obvious where housekeeping procedures or manufacturing protocols need to be increased or changed within the department.
 
Time for the electronics industry to clean up its act?
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Written by Hunter Paterson, Product Manager, Teknek   
Tuesday, 24 June 2008
Research has shown that 80% of contaminants are introduced in to a “clean area” by people and products, 15% is generated by the products themselves and 5% is actually produced by the room and filtration system.
 
Wafer-level cavity package with via-through pad interconnects
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Written by Giles Humpston   
Monday, 16 June 2008
The continued drive toward solid state imagers with greater pixel numbers and smaller pixels adversely affects yields, particularly through physical contamination during assembly of the camera module.
 
Tools & Methods for Lean Production Management in EA
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Written by Dr. T. Nguyen & Vern Harrison   
Monday, 16 June 2008

Lean manufacturing is far from a new concept, and many within the electronics assembly (EA) industry are already familiar with the principles and concepts behind it.

 
Nanotechnology and mathematical methods for high-performance thermal interface materials
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Written by Sara N. Paisner, PhD   
Monday, 16 June 2008
Higher power chips have resulted from a variety of new developments in the electronics industry.

 

 
Improving print performance using area ratio sensitivity analysis
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Written by Chris Anglin   
Monday, 09 June 2008
The purpose of a solder paste print evaluation is to observe variation in transfer efficiency to the assembly process under conditions that permit careful scrutiny.
 
Case Study: Technology partnership for effective RFID system solutions
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Written by Dipl.-Ing. (FH) Florian Hierl   
Wednesday, 21 May 2008
The market for contactless labels has passed through the trough and out the other side—RFID is gaining momentum again: In 2007, 144 million RFID tags were sold in the EU alone.
 
Challenges for high density PoP (package-on-package) utilizing SoP (solder-on-pad)
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Written by Joanna Kristine Wildhart and Moody Dreiza   
Wednesday, 14 May 2008
This paper covers the surface mount and package stacking assembly challenges related to high density package-on-package (PoP) utilizing solder-on-pad (SOP) technology.
 
Thermal profiling optimizes printed circuit board assembly
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Written by Etienne Witte and Paul Austen   
Wednesday, 07 May 2008
This article describes thermal profiling hardware and process management software solutions as used at EMS provider Axiom Electronics LLC to meet the thermal profiling challenges of today’s microelectronics environment.
 
Cleaning process integration of cleaning material with cleaning equipment
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Written by Mike Bixenman and Steve Stach   
Wednesday, 30 April 2008

Innovative electronic assembly designs strive to increase functionality over smaller surface areas. Highly dense circuit assembly designs increase the cleaning challenge.

 
Reducing cost in the EMS supply chain through niche sourcing
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Written by Dawn Poirier   
Wednesday, 16 April 2008

The EMS industry has created many business models, including those where OEMs provide value-added assembly services in addition to a proprietary product.

 
Process requirements for high density SMD placement
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Written by Sjef van Gastel   
Wednesday, 09 April 2008

As the drive towards assembly miniaturization continues and surface mount technology matures, components are becoming ever smaller and thinner.

 
Lead free HASL
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Written by T. Scimeca, G. Sikorcin, and T. Lentz   
Wednesday, 02 April 2008

The solder surface produced on bare printed circuit boards by hot air solder leveling (HASL) has been used extensively as a solderable finish for many years.

 
Comparing techniques for temperature-dependent warpage measurement
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Written by Dr. Jiahui Pan, Ryan Curry, Neil Hubble and Dr. Dirk A. Zwemer   
Wednesday, 05 March 2008

Three full-field optical techniques, shadow moiré, fringe projection, and digital image correlation (DIC), are used to measure temperature-dependent warpage....

 
Full metal TIMs
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Written by Robert N. Jarrett, Jordan P. Ross, Ross Berntson   
Wednesday, 05 March 2008

Metal thermal interface materials (TIMs) offer substantially higher thermal conductivity than other commercially available TIMs.

 
Pin in paste stencil design for notebook mainboard
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Written by Atilim Demirtas   
Wednesday, 05 March 2008

This paper examines the construction of a notebook mainboard with more than 2000 components and no wave soldering required.

 
Placement optimisation in a lean manufacturing environment
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Written by Pierre Chatain   
Wednesday, 06 February 2008

Tier 2 and Tier 3 EMS companies face increasing pressure from competition in low-cost manufacturing countries to produce assembled boards at lower cost, with increased complexity and to tighter deadlines.

 
Optimizing thermal and mechanical performance in PCBs
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Written by Alex Mangroli and Kris Vasoya   
Friday, 04 January 2008

Engineers are always striving to make a lighter, faster and stronger PCB.

 
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