Electronic assembly cleaning processes are becoming increasingly more complex because of global environmental mandates and customer-driven product performance requirements.

Few things strike more dread in the hearts of technical service personnel than the words "Is your flux compatible with material 'XYZ'?"

The continuing trend for the miniaturisation of portable electronic devices, combined with the demand for ever-greater functionality from those devices, has driven many surface mount designers away from the traditional SMT leaded package selections of PLCC, QFP, TSOP etc, and towards packages with an area grid array footprint.

Part 1—Issues in hot air solder levelling (HASL).

The various aspects of the solder joint formation from a process, metallurgical and risk management perspective are addressed in this three-paper series.

Lead-free processes for reflow and wave soldering are well documented, but this is not the case for hand soldering, which is still used for specialised electronic products. This article describes the selection of solder and board finishes that suit hand soldering and important issues affecting the choice.

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Increased functionality and smaller devices are significant drivers in innovative packaging designs.

This article examines the key sources of contamination, how it can be measured and what can be done to negate its effect.

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A single speck of dust or a fibre is enough to halt an entire production line, costing significant sums in product wastage and manufacturing downtime.

Innovative electronic assembly designs strive to increase functionality over smaller surface areas. Highly dense circuit assembly designs increase the cleaning challenge.

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With this high conductivity, these metal TIMs offer the lowest thermal interface resistance, enabling design of higher power and smaller electronic devices.

The author examines Europlacer’s new iineo pick and place system and how its Integrated Intelligence contributes towards a lean manufacturing environment.

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We are delighted to bring you this year-end roundup from some of the leading distributors around the world.

Engineers are always striving to make a lighter, faster and stronger PCB.

As consumers continue to push electronics manufacturers for smaller yet higher functioning products, packaging engineers must keep pace with the development of devices that can meet these demands.

This paper describes the PoP process requirement in general, the impact on mechanical reliability using different pad layouts and with/without underfill.

Board designers are constrained from developing fully optimal boards in the current so-called ‘Chip Packaging 1.0’ environment, and there is a clear need to change.

The design rules, hole size and other factors associated with intrusive reflow defect elimination will be outlined and compared with the intrusive reflow requirements in the latest IPC 610-D standard.

This new era of lead-free solder marks the transition of solder from faithful servant of the electronics assembly to technological nemesis.