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Wafer-level solder sphere placement and its implications

Technical Articles

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There are three main packaging technologies used by the semiconductor industry today to create solder bumps on wafers: paste printing, electroplating, or sphere dropping1. The choice between these technologies is highly influenced by the following criteria: the bump size & pitch requirements, cost and overall yield. As the bumping industry evolves, many of the deficiencies and trade-offs associated with the three bumping technologies are no longer acceptable. As a consequence, a significant transition is occurring toward a fourth bumping alternative: solder sphere placement2. This technique offers wide flexibility in bump size (40-760 µm), very high bump yields (>>99%) and low cost (sphere price dominated).

Introduction 

Figure 1. Ultra-SB2™ solder sphere placement tool.
Figure 1. Ultra-SB2™ solder sphere placement tool.
Solder bumping is often separated into several different categories: flip chip bumping (FC), wafer level chip scale packaging (WLCSP) and ball grid array (BGA). This categorization and affiliated nomenclature is partially based on the solder bump size and the type of equipment used to create the bump. Pushing the limits of each of the three traditional bumping technologies has allowed some overlap between these bumping classifications. But for the most part, volume manufacturing of flip chip, WLCSP, and BGA bumps are carried out using different processes steps on different types of equipment. Solder sphere placement is a technique that has been shown to completely bridge this technology gap. The basic principle of this technology is to simultaneously pick up preformed solder spheres using a patterned vacuum plate and then accurately place them onto the bond pads of the wafer.

The solder sphere placement technique allows a single technology to be used for an array of different bumping applications. These include:

  • All wafer sizes from 100 to 300 mm and fan-out substrates
  • All solder alloys (lead based, lead-free, polymer core)
  • FC, WLCSP, and BGA bump sizes (60-760 µm spheres)

This up-and-coming technology has been associated with several different names in the literature. These include: gang ball placement, solder ball transfer, wafer level solder sphere transfer, ultra solder ball bumping, and solder sphere placement.

The versatility of this technology can be further enhanced by coupling several other technologies into the solder sphere placement system. These include adding: 2D inspection capabilities, single sphere removal and replacement capabilities (repair and rework), and in-situ solder reflow (inert atmosphere hotplate).

The ultimate solder sphere placement system incorporates all of these discrete technologies into a single tool in order to increase versatility and assure high yields. The final configuration of the tool is often dictated by the product distribution (flip chip vs WLCSP vs BGA volumes).

Wafers or substrates for WLCSP and BGA applications have relatively large solder bumps and have relatively few interconnects compared to flip chip applications. These larger spheres are placed in extremely high yields by the solder sphere placement tool and the added expense of incorporating inspection and rework capabilities might not be justified. High I/O flip chip applications, on the other hand, often require very high bump yields in order to achieve high die yields. In these applications, integration of all the options makes good economical and throughput sense.

The recent availability of highly uniform solder spheres at lower costs has allowed the technique of solder sphere placement to expand within the industry. Typical lead-free spheres (SAC alloys) range in price between $25-50 per million when purchased in volume. As the volume of sphere consumption continues to increase, the cost will continue to come down. Spheres of other alloys, including polymer core and copper core spheres, are also starting to become more prevalent within the industry as alternatives to SAC alloys.

Process flow 

A predetermined number of spheres are automatically dispensed into a sphere reservoir (Figure 2). The amount of spheres in this reservoir is important in order to achieve high transfer yields. This value is approximately 20-30% more than the number of I/O on the wafer.

Figure 2. Solder sphere reservoir filled with solder spheres.
Figure 2. Solder sphere reservoir filled with solder spheres.

 The fixture which picks up the spheres consists of two main components: a vacuum head which is mounted to a high precision x-y-z translation stage and a tooling plate which contains small holes that is mechanically mounted to the vacuum head (Figure 3).

Figure 3. Sphere placement head positioned over the solder sphere reservoir.
Figure 3. Sphere placement head positioned over the solder sphere reservoir.

The tooling plate is patterned with openings that correspond directly with the locations of the I/O pads on the wafer. This tooling is created using similar methods to that of making a nickel-plated surface-mount stencil. There are a large number of vendors who can now manufacture these stencils using electroforming techniques. The size of openings in the tooling plate is designed to be slightly smaller than the size of spheres that will be placed onto the wafer.

The sphere placement head is then lowered onto the sphere reservoir and the vacuum is applied to the vacuum port (Figure 4). The vacuum alone is not sufficient to efficiently transport and relocate the solder spheres into each opening in the stencil template. The application of ultrasonics is applied to the reservoir to aid in sphere movement.

Figure 4. Sphere placement head lowered onto sphere reservoir. Vacuum and ultrasonics applied to reservoir.
Figure 4. Sphere placement head lowered onto sphere reservoir. Vacuum and ultrasonics applied to reservoir.

Optimization of the ultrasonic amplitude and frequency, in addition to the vacuum, is required for each spheres size and I/O density in order to maximize sphere relocation to the template. Even with this optimization, an unwanted sphere can occasionally adhere to the stencil. This is commonly a result of static electricity. Removal of these extra spheres is accomplished passing the head over a deionizing air knife (Figure 5).

Figure 5. Shear placement head with solder spheres passing over deionizing air knife to remove any excess spheres.
Figure 5. Shear placement head with solder spheres passing over deionizing air knife to remove any excess spheres.

The placement head is then moved over to the transfer station within the tool. A prefluxed wafer has been pre-positioned from a wafer cassette onto the vacuum chuck at this station (Figure 6). The application of tacky flux is applied in a separate tool prior to being loaded into the sphere placement tool. For WLCSP and BGA applications, screen-printing or stencil printing are used to apply this flux. For flip chip applications, spin coating is used to apply the flux. The important criteria for all applications include flux thickness and viscosity.

Figure 6. A pre-fluxed wafer is automatically placed onto the vacuum wafer chuck.
Figure 6. A pre-fluxed wafer is automatically placed onto the vacuum wafer chuck.

The solder transfer head is then moved over the wafer chuck and a bidirectional optical sensor is extended in between the head and the chuck (Figure 7). This inspection system allows the spheres within the apertures of the stencil template to be aligned to the bond pads on the wafer. In addition to alignment, this sensor performs a 2D scan of the stencil template to confirm that all apertures contain a solder sphere and also inspects for unwanted stray spheres that may still be attached to the template. The tool software can then make a decision based on user criteria to continue to the transfer step, return further cleaning at the air knife station, or go completely back to the sphere pickup station to fill in empty apertures with spheres.

Figure 7. Optical sensor extended between the wafer and placement head. Aligning the template to the wafer and also inspecting for missing or unwanted spheres.
Figure 7. Optical sensor extended between the wafer and placement head. Aligning the template to the wafer and also inspecting for missing or unwanted spheres.

The solder placement head is then lowered toward the wafer until the solder spheres penetrate the flux and touch the wafer bond pads (Figure 8). The mechanical downward force is adjusted to help drive the spheres onto the pads. The vacuum is then released and a N2 back pressure is applied to the placement head to assist in releasing the spheres.

Figure 8. Tooling head lowered on wafer to bring spheres into contact with the fluxed wafer pads.
Figure 8. Tooling head lowered on wafer to bring spheres into contact with the fluxed wafer pads.

The head is then raised and the optical inspection sensor is reinserted over the wafer, and the wafer is scanned to quantify transfer yields (Figure 9). This scan will document the x-y coordinates of any missing or misplaced spheres that may have moved after the transfer process.

Figure 9. Raise placement head and insert optical sensor over wafer.
Figure 9. Raise placement head and insert optical sensor over wafer.

For flip chip applications, where high bump yields are an absolute requirement to give high die yields, integration of rework/repair capabilities is critical. It is common for high-end applications, such as microprocessors, to have hundreds of interconnects per die. Even small bump yield losses can translate into high die yield losses.

A repair head, which is based on the SB2 ™ sphere bumping process3, is used to repair any defects identified in the 2D inspection (Figure 10). For missing bumps, a sphere is dropped onto the pad where the bump is missing. This process has no mechanical contact with the wafer and solder bumps are deposited at a rate of 6-10 spheres per second. For misplaced or damaged spheres, the capillary head of the SB2 tool is lowered over the sphere, the capillary heated, and a vacuum is applied to the tube, which removes the sphere. In both cases a laser pulse can be added to help liquify the flux or melt the solder sphere.

Figure 10. SB2 repair head positioned over a pad with a missing solder bump.
Figure 10. SB2 repair head positioned over a pad with a missing solder bump.

The wafer is then ready for final reflow. For most WLCSP and BGA devices the wafers are placed back into the wafer cassette. Once all 25 wafers are bumped, the cassette is moved over to a linearconduction oven for reflow. Alternatively the wafers can be moved over to a reflow chamber located within in the tool (Figure 11). This is more common for fine pitch flip chip devices.

Figure 11. Solder bumps reflowed on heated vacuum chuck.
Figure 11. Solder bumps reflowed on heated vacuum chuck.

After reflow, the wafers are placed back into the process cassette and cleaned in a batch process using a combination of ultrasonics, solvents and water rinsing (Figure 12).

 

Figure 12. Bumped, reflowed and cleaned wafer.
Figure 12. Bumped, reflowed and cleaned wafer.

Conclusions 

The wafer level solder sphere placement tool can perform flip chip, WLCSP, and BGA bumping operations (Figure 13). The configuration of the tool is dictated by the product distribution (Tables 1 and 2). Defects in the ppm range result in die yields greater than 99%. Wafer throughputs are between 20-45 wafers per hour.

Figure 13. SEM image of 60 μm flip chip bumps and 300 μm WLCSP solder bumps.
Figure 13. SEM image of 60 μm flip chip bumps and 300 μm WLCSP solder bumps.

 

Table 1. Process steps for WLCSP and BGA applications.
Table 1. Process steps for WLCSP and BGA applications.
 
Table 2. Process steps for flip chip applications.
Table 2. Process steps for flip chip applications.

Acknowledgements 

The authors would like to thank all the engineers and technicians of PacTech for their help in developing the solder sphere placement technology.

References 

  1. D. S. Patterson, P. Elenius, and J. Leal, “Wafer Bumping Technologies – A comparative analysis of Solder Deposition Processes and Assembly Considerations”, EEP Vol. 19-1, Advances in Electronic Packaging, Hawaii, 1997, pp. 337-351.
  2. M. Whitmore, M. Staddon, D. Manessis: “Development of a Low Cost Wafer-Level Bumping Technique”, International Wafer-Level Packaging Conference, 2004.
  3. J. Ling, T. Strothmann, D. Stepniak, P. Elanius, “Flex-On-Cap Solder Bump for 300mm Wafer”, Semicon, Singapore, 2001.
  4. T. Flynn, C.W. Argento, and J.Obrien, “Electro-plated flip chip Wafer Bumping Interconnect Technology Solutions for the 21st Century”, Proceedings of International Symposium on Microelectronics, Chicago, Illinois, October 26-28, 1999, pp. 8-12.
  5. K. Tatsumi, K. Shimokawa, E. Hashino, Y. Ohzeki, T. Nakamori, and M.Tanaka, “Micro-Ball Bumping Technology for flip chip”, The International Journal of Microcircuits and Electronic Packaging, Volume 22, Number 2, Second Quarter 1999 (ISSN 1063-1674), pp.127-136.
  6. Andrew Strandjord, Thorsten Teutsch, Axel Scheffler, Thomas Oppert, Ghassem Azdasht, and Elke Zakel, “WLCSP Production Using Electroless Ni/Au Plating and Wafer Level Solder Sphere Transfer Technology”, IWLPC, San Jose, CA, October 14th, 2008.
  7. Andrew Strandjord “Solder Ball Transfer for flip chip and WLCSP”, Advanced Packaging, March 19, 2008.
  8. P. Kasulke, W. Schmidt, L. Titerle, H. Bohnaker, T. Oppert, E. Zakel, “Solder Ball Bumper SB2-A flexible manufacturing tool for 3-dimensional sensor and microsystem packages”, Proceedings of the International Electronics Manufacturing Technology Symposium (22nd IEMT), Berlin, April 27-29, 1998.
  9. Elke Zakel, Lars Titerle, Thomas Oppert, Ronald G. Blankenhorn, “High Speed Laser Solder Jetting Technology for Optoelectronics and MEMS Packaging”, Proceedings of the International Conference on Electronics Packaging (Tokyo, Japan), Apr. 17-19, 2002.

Andrew Strandjord is senior manager of advanced packaging at PacTech USA. He received his Ph.D. in organic chemistry from the University of Minnesota.
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Mr. Oppert is vice president global sales & marketing at PacTech in Nauen, Germany. He earned a master’s degree in electrical engineering from the Technical University of Berlin in 1995. Thomas Oppert has co-authored more than 50 technical papers related to semiconductor packaging. This e-mail address is being protected from spambots. You need JavaScript enabled to view it

 

Dr. Thorsten Teutsch is president of PacTech-USA. He received his Ph.D. in physical chemistry and surface science from Fritz-Haber Institute of the Max Planck Society.
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Mr. Ghassem Azdasht is co-founder and CTO of PacTech GmbH. He studied mechanical engineering and laser technologies at the Technical University Berlin. Mr. Azdasht has authored of over 100 publications and patents related to wire bonding, flip chip, and laser assembly. This e-mail address is being protected from spambots. You need JavaScript enabled to view it

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