7.8 – IC packaging and interconnection technologies’ 4th dimension challenge
Written by obwain
Tuesday, 04 September 2007 14:57
Over the course of the last five or six years there has been an explosion of innovation in the realm of IC packaging. Most of the attention has been focused on methods and structures that allow for ever greater density and the pursuit of stacked packaging concepts or, as they have come to be known collectively, 3D packaging. The current third dimension paradigm was cleverly identified as the ‘More than Moore alternative to ‘More of Moore. The latter was an obvious reference to ‘Moores Law, which predicted the doubling of transistors on ICs every 18 – 24 months based on a reduction in feature sizes predicated on constant improvement in semiconductor processing methods, most importantly in the area of lithography. With semiconductor technology once again approaching the predicted boundary of its limits (it has been predicted before, more than once), many scientists and engineers believe that this time both the physical limits and the limits of physics are for real. That said, experience says that there is need to leave open the door to an unforeseen breakthrough that could push the limits out a bit further, but there is likely going to be a point of diminishing returns. A number of semiconductor manufacturers have already acknowledged this by turning back and using higher yielding, earlier generation technologies rather than the leading edge, in order to improve margins and competitiveness. What they are concluding is that it makes more sense to solve transistor density challenges with finesse in IC packaging rather than brute force lithographic gains. As a result, IC packaging is now becoming the solution of choice in many design situations.
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This column appeared in Global SMT & Packaging 7.8, August 2007.