Molded underfill process for the SiP
Written by Tae Hyun Kim, Ki Chan Kim, et al, Samsung Electro-Mechanics Co., Ltd.
Friday, 09 January 2009 16:31
For our application and experiment, a new underfilling process, molded underfill (MUF), is being investigated. A few companies have already tried to develop this process using one flip chip. In this application, we are molding three flip chips into the underfill process. The test vehicle consists of three 3.5 x 3.5 mm flip chips, one saw filter and several passive components. The package dimensions are 11 x 11 mm, and the substrate has four layers with a thickness of 0.3 mm. Two classes of daisy chin chips are used as dummies to perform DC electrical tests.
Vital process factors are determined, then the process conditions are optimized. Afterwards, a comparison is made between the reliability level of a MUF sample and a conventional underfilled and molded sample. Tthe reliability test of the MUF sample shows good promise.
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