Articles & Papers
Pushing the barriers of wafer level device integration
Tuesday, July 8, 2008
—Techsearch has predicted a compound annual growth rate of more than 24% for wafer-level packages between 2005 and 2010. Contract electronics manufacturers and original design manufacturers face a range of handling problems when using these small silicon devices in assemblies.
White paper: Bumping BGAs using solder paste printing process for RFI shields packaging
Friday, January 26, 2007
—One manufacturing process used to attach RFI shields for medical applications/cellular phone circuit board assemblies consists of "snapping" the shell-like shields onto solder spheres that are soldered to printed circuit board [PCB] pads.
7.2 – Evaluation of wafer bumping stencils
Wednesday, March 7, 2007
—In order to better characterize the performance of wafer bumping stencils, a novel solder transfer ratio has been defined that relates the amount of solder paste volume transferred to a wafer to the actual stencil aperture volume.
Cost reduction of wafer level packaging
Monday, August 17, 2009
—Solid state imagers are being incorporated in an ever-expanding diversity of products.
Wafer–level cavity package with via–through pad interconnects
Monday, June 16, 2008
—The continued drive toward solid state imagers with greater pixel numbers and smaller pixels adversely affects yields, particularly through physical contamination during assembly of the camera module.
Metal–based wafer level packaging
Monday, August 17, 2009
—Metal based wafer bonding for WLP has several advantages, including
enhanced hermeticity, and it facilitates vertical integration.
Molded underfill process for the SiP
Friday, January 9, 2009
—For our application and experiment, a new underfilling process, molded underfill (MUF), is being investigated.
Wafer-level solder sphere placement and its implications
Friday, August 6, 2010
—There are three main packaging technologies used by the semiconductor industry today to create solder bumps on wafers: paste printing, electroplating, or sphere dropping.
Integrated testing, modeling and failure analysis of CSPnl for board level reliability
Friday, July 9, 2010
—The wafer level chip scale package (WLCSP) is gaining popularity for its performance and for its ability to meet miniaturization requirements of certain electronic products, especially handheld devices like cell phones.
PACTECH at NEPCON CHINA 2012
Pac Tech - Packaging Technologies is a worldwide leader in both Wafer Level Bumping & Packaging Services and in Advanced Packaging Equipment Manufacturing.
Pac Tech has over 15 years of experience in the industry and has manufacturing sites all around the world, including: Germany, United States, Japan, and Malaysia. These sites can supply both engineering and prototyping services, as well as high volume production.
For more information, please visit: www.pactech.de
Interview: Poornima Shenoy, president of the India Semiconductor Association
Debasish Choudhury interviews Poornima Shenoy, president of the India Semiconductor Association (ISA)
GPD GLOBAL at APEX IPC Expo 2012
GPD demonstrated at the APEX IPC Expo 2012 in San Diego, the PCD and MicroDot technologies on its MAX Series platform. MAX Series dispensing systems offer high accuracy, precision dispensing over a wide range of applications. The MAX Series platforms are ideal for die attach, underfill, MEMS, micro-volume conductive adhesive and paste applications. Max Series equipped with Micro-volume technology enables dispensing for 0201 components as well as die attach adhesives. Further expanding the Max Series capabilities with the continuously volumetric PCD dispense pump yields outstanding results with underfills, encapsulation and LED applications.
For more Information, please visit: www.gpd-global.com
Video Editor: Elisangela Dahlke
Juki at APEX 2009
Juki president Bob Black talks about the new equipment Juki brought to IPC APEX Expo 2009: the JX-100 15,000 pph entry-level placement machine, an upgraded 2080 fine pitch placer, the highest speed soldering machine on the market, and their new flexible, entry-level W510 soldering machine.
Bergen Systems Pvt Ltd at COMPONEX NEPCON India 2009
Pradeep Kaura of Bergen Systems Pvt Ltd introduces a new placement system and in-circuit tester.
MIRTEC at SMT/HYBRID/PACKAGING 2010
David Bennett, managing director of MIRTEC Europe, shows off the MS-11 high speed inline solder paste inspection system and the MV-7XI with the award-winning integrated Intelli-Scan laser inspection system for detecting lifted leads and coplanarity.
Milara at IPC APEX Expo 2011
Stephen Brodeur introduces the fully inline Milara TouchPrint stencil printer series, which is now in full release. It features the fully integrated CyberOptics SE500 post-print inspection technology and Asymtek dot dispensing option.
Nordson Asymtek at IPC APEX Expo 2013
Trevor Galbraith interviews Dan W. Ashley, Market Specialist Printed Circuit Board Assembly of Nordson Asymtek at Apex Expo 2013
Valor at IPC APEX Expo 2010
Julian Coates from the Valor division of Mentor Graphics introduces their complete factory-level control system.
From our Columnists
Wafer level packaging and the third dimension
Tuesday, September 23, 2008
Depending on how liberal one is in their definition of what a wafer
level package is, the technology is either entering its second, third
or perhaps even its fourth or fifth decade of use.
IC packaging technology retrospective
Monday, March 2, 2009
—All IC packaging technology structures since the invention of the
integrated circuit itself have been tasked to perform, at a minimum,
the simple and fundamental tasks of interconnecting and protecting the
semiconductor die and making it useful for interconnection at the next
7.7 – IC packaging
Thursday, August 16, 2007
—While the glamour of the integrated circuit has diminished little over the nearly five decades of its existence, it has become increasingly clear in the last several years that the performance of semiconductor chips is being gated by the IC package.
PiP, PoP and PuP
Monday, April 6, 2009
—Since the beginning, all IC packages have been designed to perform the
basic tasks of interconnecting and protecting the semiconductor die and
making it useful for interconnection at the next level.
6.2 – Standards for IC packages: blessing or burden?
Wednesday, February 1, 2006
—Since shortly after the introduction of the first ICs there has been an effort to put in place standards for IC packages.
Is a standard lead pitch for components possible?
Tuesday, July 3, 2012
—IC packaging technology has led the march of progress since the earliest days of the electronics industry. Decisions made by those responsible for packaging integrated circuits have a ripple effect that extends to the rest of the electronics industry.
3d: Benefits and challenges
Thursday, September 26, 2013
—While a substantial amount of electronic interconnection has been performed in the 3rd dimension throughout the history of electronics, the pursuit of 3D interconnections at chip level is relatively new, even though some prescient inventors in the earliest days of the semiconductor industry foresaw its potential benefit.
Microelectronics Assembly and Packaging (MAP) workshop 2008 review
Monday, February 9, 2009
—The 8th International workshop on microelectronics assembly and
packaging technologies was held in late November of last year and
continues to be one of the best-kept open secrets of the IC packaging
7.8 – IC packaging and interconnection technologies’ 4th dimension challenge
Tuesday, September 4, 2007
—Over the course of the last five or six years there has been an explosion of innovation in the realm of IC packaging.
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Digi-Key debuts innovative mobile app for Freescale
Friday, April 11, 2014—Global electronic components distributor Digi-Key Corporation, the industry leader in electronic component selection, availability and delivery, has collaborated with Freescale® Semiconductor, a global leader in embedded processing solutions, to create the electronic component industry’s first distributor/supplier collaborative mobile application.
CircuitWorks flux dispensing pens/syringes and flux removal pens from Intertronics
Monday, April 7, 2014—The CircuitWorks range of handy pens and syringes for electronic prototyping, rework and repair of circuit boards includes flux dispensing and flux removal in their range, now available ex stock from Intertronics.
Explained Peter Swanson, M.D. of Intertronics: “CircuitWorks flux dispensing pens provide a convenient and clean way to apply a variety of flux types commonly used in prototype, rework and repair and low volume production – with controlled and exact application.
Fixed frequency synthesizer features low phase noise at 10.625GHz
Wednesday, April 2, 2014—Z-Communications, Inc. announces a new RoHS compliant Fixed Frequency Synthesizer model SFS10625E-LF. The SFS10625E-LF is a single frequency PLL solution that is pre-programmed to operate at 10.625GHz. This fixed frequency device utilizes ceramic resonator topology to achieve integrated RMS noise performance of better than 0.4° while consuming less than 500mW of power.
Needle valve offers high dispensing precision
Wednesday, April 2, 2014—Dymax Corporation’s Model 485 pneumatic, normally closed needle valve is designed to deliver precise dots or very fine beads of low- to high-viscosity fluids. The valve’s stroke adjustment allows for fine-tuning of the dispense volume, ensuring precise and consistent deposits. Users are able to dispense from pressurized cartridges, bottles, and pails making the valve compatible with most standard fluid packages and delivery systems.
Henkel Develops new suite of encapsulant materials for maximum device protection
Tuesday, April 1, 2014—Today’s automotive and handheld applications are increasingly exposed to damaging environmental contaminants. Protecting devices within these products from chemicals, fluids and other environmental conditions is critical to ensuring long-term reliability. To this end, the Electronics Group of Henkel has developed and made commercially available three new encapsulant materials that offer exceptional protection for modern devices.
Mentor Graphics announces the Questa X-Value verification solution
Tuesday, April 1, 2014—Mentor Graphics Corp. (NASDAQ: MENT), announced availability of a new solution for X-value verification in register transfer level (RTL) and gate level designs. X-values are symbols that represent unknown voltage levels of signals in digital IC designs. The latest version of the Questa® Verification Platform links simulation and formal verification capabilities to deliver complete X-value analysis and debug, which helps an IC design team avoid the risk of silicon and simulation failure.
Engineered Material Systems introduces 535-10M-49 UV cure adhesive
Monday, March 31, 2014—Engineered Material Systems, a leading global supplier of electronic materials for circuit assembly applications, debuts its 535-10M-49 UV cured epoxy adhesive formulated for disk drive, camera module, optoelectronic and circuit assembly applications. The material contains a secondary thermal cure initiator that cures as low as 110°C for shadowed areas.
Thermally stable, two part epoxy meets NASA low outgassing specifications
Monday, March 31, 2014—Master Bond EP30-3LO is a two component epoxy system offering optical clarity, high temperature resistance, and NASA low outgassing approval. This combination of properties enables it to be suitable for bonding, sealing, coating and encapsulation applications in the aerospace, electronic, optical and optoelectronic industries.
Silicon Avalanche Photodiodes with low bias operation
Thursday, March 27, 2014—APDs are high sensitivity photodiodes with low terminal capacitance, whose internal gain mechanism enables reliable measurements to be taken even at very low light levels. These APDs are supplied in compact, high reliability TO-18 packages. Their special low bias operation means that voltages of less than 200V can be used whilst still maintaining stable operation.
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