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Special Topics: Advanced packaging
Articles & Papers
Pushing the barriers of wafer level device integration
Tuesday, July 8, 2008Techsearch has predicted a compound annual growth rate of more than 24% for wafer-level packages between 2005 and 2010. Contract electronics manufacturers and original design manufacturers face a range of handling problems when using these small silicon devices in assemblies.

White paper: Bumping BGAs using solder paste printing process for RFI shields packaging
Friday, January 26, 2007One manufacturing process used to attach RFI shields for medical applications/cellular phone circuit board assemblies consists of "snapping" the shell-like shields onto solder spheres that are soldered to printed circuit board [PCB] pads.
7.2 – Evaluation of wafer bumping stencils
Wednesday, March 7, 2007In order to better characterize the performance of wafer bumping stencils, a novel solder transfer ratio has been defined that relates the amount of solder paste volume transferred to a wafer to the actual stencil aperture volume.

Cost reduction of wafer level packaging
Monday, August 17, 2009Solid state imagers are being incorporated in an ever-expanding diversity of products.

Wafer–level cavity package with via–through pad interconnects
Monday, June 16, 2008The continued drive toward solid state imagers with greater pixel numbers and smaller pixels adversely affects yields, particularly through physical contamination during assembly of the camera module.
Metal–based wafer level packaging
Monday, August 17, 2009Metal based wafer bonding for WLP has several advantages, including enhanced hermeticity, and it facilitates vertical integration.

Molded underfill process for the SiP
Friday, January 9, 2009For our application and experiment, a new underfilling process, molded underfill (MUF), is being investigated.

Wafer-level solder sphere placement and its implications
Friday, August 6, 2010There are three main packaging technologies used by the semiconductor industry today to create solder bumps on wafers: paste printing, electroplating, or sphere dropping.
Integrated testing, modeling and failure analysis of CSPnl for board level reliability
Friday, July 9, 2010The wafer level chip scale package (WLCSP) is gaining popularity for its performance and for its ability to meet miniaturization requirements of certain electronic products, especially handheld devices like cell phones.
 
Videos
PACTECH at NEPCON CHINA 2012
Pac Tech - Packaging Technologies is a worldwide leader in both Wafer Level Bumping & Packaging Services and in Advanced Packaging Equipment Manufacturing. Pac Tech has over 15 years of experience in the industry and has manufacturing sites all around the world, including: Germany, United States, Japan, and Malaysia. These sites can supply both engineering and prototyping services, as well as high volume production. For more information, please visit: www.pactech.de
Interview: Poornima Shenoy, president of the India Semiconductor Association
Debasish Choudhury interviews Poornima Shenoy, president of the India Semiconductor Association (ISA)
GPD GLOBAL at APEX IPC Expo 2012
GPD demonstrated at the APEX IPC Expo 2012 in San Diego, the PCD and MicroDot technologies on its MAX Series platform. MAX Series dispensing systems offer high accuracy, precision dispensing over a wide range of applications. The MAX Series platforms are ideal for die attach, underfill, MEMS, micro-volume conductive adhesive and paste applications. Max Series equipped with Micro-volume technology enables dispensing for 0201 components as well as die attach adhesives. Further expanding the Max Series capabilities with the continuously volumetric PCD dispense pump yields outstanding results with underfills, encapsulation and LED applications. For more Information, please visit: www.gpd-global.com Video Editor: Elisangela Dahlke
Juki at APEX 2009
Juki president Bob Black talks about the new equipment Juki brought to IPC APEX Expo 2009: the JX-100 15,000 pph entry-level placement machine, an upgraded 2080 fine pitch placer, the highest speed soldering machine on the market, and their new flexible, entry-level W510 soldering machine.
Bergen Systems Pvt Ltd at COMPONEX NEPCON India 2009
Pradeep Kaura of Bergen Systems Pvt Ltd introduces a new placement system and in-circuit tester.
OKI at NEPCON South China 2014
We congratulate OK International's Paul Wood at Nepcon South China for winning an award for their latest solder cleaning solution 'Solder Bee' and discusses how OKI respond to the rapid advances in new packages launched onto the market.
MIRTEC at SMT/HYBRID/PACKAGING 2010
David Bennett, managing director of MIRTEC Europe, shows off the MS-11 high speed inline solder paste inspection system and the MV-7XI with the award-winning integrated Intelli-Scan laser inspection system for detecting lifted leads and coplanarity.
Milara at IPC APEX Expo 2011
Stephen Brodeur introduces the fully inline Milara TouchPrint stencil printer series, which is now in full release. It features the fully integrated CyberOptics SE500 post-print inspection technology and Asymtek dot dispensing option.
Nordson Asymtek at IPC APEX Expo 2013
Trevor Galbraith interviews Dan W. Ashley, Market Specialist Printed Circuit Board Assembly of Nordson Asymtek at Apex Expo 2013
From our Columnists
Wafer level packaging and the third dimension
Tuesday, September 23, 2008

Depending on how liberal one is in their definition of what a wafer level package is, the technology is either entering its second, third or perhaps even its fourth or fifth decade of use.

IC packaging technology retrospective
Monday, March 2, 2009All IC packaging technology structures since the invention of the integrated circuit itself have been tasked to perform, at a minimum, the simple and fundamental tasks of interconnecting and protecting the semiconductor die and making it useful for interconnection at the next level.

7.7 – IC packaging
Thursday, August 16, 2007While the glamour of the integrated circuit has diminished little over the nearly five decades of its existence, it has become increasingly clear in the last several years that the performance of semiconductor chips is being gated by the IC package.

PiP, PoP and PuP
Monday, April 6, 2009Since the beginning, all IC packages have been designed to perform the basic tasks of interconnecting and protecting the semiconductor die and making it useful for interconnection at the next level.

6.2 – Standards for IC packages: blessing or burden?
Wednesday, February 1, 2006Since shortly after the introduction of the first ICs there has been an effort to put in place standards for IC packages.
Is a standard lead pitch for components possible?
Tuesday, July 3, 2012IC packaging technology has led the march of progress since the earliest days of the electronics industry. Decisions made by those responsible for packaging integrated circuits have a ripple effect that extends to the rest of the electronics industry.

3d: Benefits and challenges
Thursday, September 26, 2013While a substantial amount of electronic interconnection has been performed in the 3rd dimension throughout the history of electronics, the pursuit of 3D interconnections at chip level is relatively new, even though some prescient inventors in the earliest days of the semiconductor industry foresaw its potential benefit.

Read more

Microelectronics Assembly and Packaging (MAP) workshop 2008 review
Monday, February 9, 2009The 8th International workshop on microelectronics assembly and packaging technologies was held in late November of last year and continues to be one of the best-kept open secrets of the IC packaging industry.

7.8 – IC packaging and interconnection technologies’ 4th dimension challenge
Tuesday, September 4, 2007Over the course of the last five or six years there has been an explosion of innovation in the realm of IC packaging.

 
 
Latest SMT Answers questions
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Latest Products
Enthone introduces EnFILL® Copper Via Fill Systems for HDI any-layer build-ups
Wednesday, October 29, 2014EnFILL® Copper Via Fill Systems have been introduced by Enthone Inc.  Specially engineered to enhance productivity of HDI any-layer build-ups, each integrated system offers a high current capacity that is production-proven to reduce cycle time by up to 40%, while reliably providing superior via fill capacity with minimal dimple.
Economical triple-channel programmable power supply from Keithley outperforms competitive supplies
Wednesday, October 29, 2014The Model 2231A-30-3 195W Triple-Channel DC Power Supply combines the advantage of greater output accuracy than competitive power supplies, with features that enhance its ease of use in circuit design and university student labs for device testing applications that require multiple power sources.
Digitaltest announces FailSim
Wednesday, October 29, 2014During the past year Digitaltest has continued to push the boundaries of performance, coverage and ease of use to a new level across all their test platforms. Digitaltest’s new developments include the AMU5 which, provides high performance 5th generation measurement capability for all our systems, New Flying Probe capabilities, enhanced CAD Translation and Quality Management Software.
Coherent announces new AVIA NX laser offering increased performance and lower cost for microelectronics packaging applications
Friday, October 24, 2014AVIA series lasers from Coherent, Inc. (Santa Clara, CA) are well established in microelectronics packaging applications, and the latest AVIA NX sets a new standard for economy, reliability and ease of use.  Specifically, these new q-switched, diode-pumped, solid-state lasers offer output powers as high as 40W at 355 nm, but with a substantially lower cost per watt than any other available product.

Sensor System accurately monitors material level in pressurized reservoirs
Thursday, October 23, 2014A new Low-Level-Sensing Reservoir System from Dymax Corporation prevents empty material reservoirs from introducing air into dispensing lines, thereby eliminating contamination during the dispensing process.  The system utilizes an adjustable sensor for use with pressurized reservoirs, and features an SB-100 controller which activates a warning when the material in the reservoir reaches a specified low level.
XJTAG releases boundary scan for Teradyne TestStation
Wednesday, October 22, 2014XJTAG, a supplier of boundary scan technology, announced the release of the XJLink2-CFM and XJLink2-CFMx. The new modules provide Teradyne users with integrated access to XJTAG’s powerful test and programming tools, operating under the control of the TestStation™ test program.
Cree Releases SPICE Models for C2M SiC Power MOSFETs
Wednesday, October 15, 2014To take full advantage of all the benefits of SiC technology, power converters must be redesigned specifically for SiC devices. SiC MOSFETs have significantly different characteristics than silicon devices, and thus require SiC-specific models for accurate circuit simulations. Cree’s behavior-based and temperature-dependent SPICE model delivers accurate simulation results without compromising speed and includes self-heating and transient thermal capabilities.
Fabrico offers OSHA HCS labelling requirements for products containing hazardous chemicals
Tuesday, October 14, 2014Fabrico, the leader in design and manufacturing services for flexible materials and advanced assembly, provides packaging and label printing of OSHA’s Hazardous Communication Standard (HCS), which requires manufacturers of products that contain potentially harmful chemicals to apply hazard information and pictograms on their packaging and labels.

SolderStar engineers a new profiling platform to ensure quality control of today’s complex technologies
Thursday, October 9, 2014With technologies constantly changing and smaller and more complex designs being developed, it poses a problem in the manufacture of quality printed circuit boards making the use of reflow oven profiling ever more important. With this in mind, SolderStar Ltd, a leading specialist manufacturer in the design and development of thermal profiling equipment for the lead-free electronics industry, has developed the DeltaProbe, a new add-on technology that ensures a quality product.
 
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