Articles & Papers
Pushing the barriers of wafer level device integration
Tuesday, July 8, 2008
—Techsearch has predicted a compound annual growth rate of more than 24% for wafer-level packages between 2005 and 2010. Contract electronics manufacturers and original design manufacturers face a range of handling problems when using these small silicon devices in assemblies.
White paper: Bumping BGAs using solder paste printing process for RFI shields packaging
Friday, January 26, 2007
—One manufacturing process used to attach RFI shields for medical applications/cellular phone circuit board assemblies consists of "snapping" the shell-like shields onto solder spheres that are soldered to printed circuit board [PCB] pads.
7.2 – Evaluation of wafer bumping stencils
Wednesday, March 7, 2007
—In order to better characterize the performance of wafer bumping stencils, a novel solder transfer ratio has been defined that relates the amount of solder paste volume transferred to a wafer to the actual stencil aperture volume.
Cost reduction of wafer level packaging
Monday, August 17, 2009
—Solid state imagers are being incorporated in an ever-expanding diversity of products.
Wafer–level cavity package with via–through pad interconnects
Monday, June 16, 2008
—The continued drive toward solid state imagers with greater pixel numbers and smaller pixels adversely affects yields, particularly through physical contamination during assembly of the camera module.
Metal–based wafer level packaging
Monday, August 17, 2009
—Metal based wafer bonding for WLP has several advantages, including
enhanced hermeticity, and it facilitates vertical integration.
Molded underfill process for the SiP
Friday, January 9, 2009
—For our application and experiment, a new underfilling process, molded underfill (MUF), is being investigated.
Wafer-level solder sphere placement and its implications
Friday, August 6, 2010
—There are three main packaging technologies used by the semiconductor industry today to create solder bumps on wafers: paste printing, electroplating, or sphere dropping.
Integrated testing, modeling and failure analysis of CSPnl for board level reliability
Friday, July 9, 2010
—The wafer level chip scale package (WLCSP) is gaining popularity for its performance and for its ability to meet miniaturization requirements of certain electronic products, especially handheld devices like cell phones.
PACTECH at NEPCON CHINA 2012
Pac Tech - Packaging Technologies is a worldwide leader in both Wafer Level Bumping & Packaging Services and in Advanced Packaging Equipment Manufacturing.
Pac Tech has over 15 years of experience in the industry and has manufacturing sites all around the world, including: Germany, United States, Japan, and Malaysia. These sites can supply both engineering and prototyping services, as well as high volume production.
For more information, please visit: www.pactech.de
Interview: Poornima Shenoy, president of the India Semiconductor Association
Debasish Choudhury interviews Poornima Shenoy, president of the India Semiconductor Association (ISA)
GPD GLOBAL at APEX IPC Expo 2012
GPD demonstrated at the APEX IPC Expo 2012 in San Diego, the PCD and MicroDot technologies on its MAX Series platform. MAX Series dispensing systems offer high accuracy, precision dispensing over a wide range of applications. The MAX Series platforms are ideal for die attach, underfill, MEMS, micro-volume conductive adhesive and paste applications. Max Series equipped with Micro-volume technology enables dispensing for 0201 components as well as die attach adhesives. Further expanding the Max Series capabilities with the continuously volumetric PCD dispense pump yields outstanding results with underfills, encapsulation and LED applications.
For more Information, please visit: www.gpd-global.com
Video Editor: Elisangela Dahlke
Juki at APEX 2009
Juki president Bob Black talks about the new equipment Juki brought to IPC APEX Expo 2009: the JX-100 15,000 pph entry-level placement machine, an upgraded 2080 fine pitch placer, the highest speed soldering machine on the market, and their new flexible, entry-level W510 soldering machine.
Bergen Systems Pvt Ltd at COMPONEX NEPCON India 2009
Pradeep Kaura of Bergen Systems Pvt Ltd introduces a new placement system and in-circuit tester.
OKI at NEPCON South China 2014
We congratulate OK International's Paul Wood at Nepcon South China for winning an award for their latest solder cleaning solution 'Solder Bee' and discusses how OKI respond to the rapid advances in new packages launched onto the market.
MIRTEC at SMT/HYBRID/PACKAGING 2010
David Bennett, managing director of MIRTEC Europe, shows off the MS-11 high speed inline solder paste inspection system and the MV-7XI with the award-winning integrated Intelli-Scan laser inspection system for detecting lifted leads and coplanarity.
Milara at IPC APEX Expo 2011
Stephen Brodeur introduces the fully inline Milara TouchPrint stencil printer series, which is now in full release. It features the fully integrated CyberOptics SE500 post-print inspection technology and Asymtek dot dispensing option.
Nordson Asymtek at IPC APEX Expo 2013
Trevor Galbraith interviews Dan W. Ashley, Market Specialist Printed Circuit Board Assembly of Nordson Asymtek at Apex Expo 2013
From our Columnists
Wafer level packaging and the third dimension
Tuesday, September 23, 2008
Depending on how liberal one is in their definition of what a wafer
level package is, the technology is either entering its second, third
or perhaps even its fourth or fifth decade of use.
IC packaging technology retrospective
Monday, March 2, 2009
—All IC packaging technology structures since the invention of the
integrated circuit itself have been tasked to perform, at a minimum,
the simple and fundamental tasks of interconnecting and protecting the
semiconductor die and making it useful for interconnection at the next
7.7 – IC packaging
Thursday, August 16, 2007
—While the glamour of the integrated circuit has diminished little over the nearly five decades of its existence, it has become increasingly clear in the last several years that the performance of semiconductor chips is being gated by the IC package.
PiP, PoP and PuP
Monday, April 6, 2009
—Since the beginning, all IC packages have been designed to perform the
basic tasks of interconnecting and protecting the semiconductor die and
making it useful for interconnection at the next level.
6.2 – Standards for IC packages: blessing or burden?
Wednesday, February 1, 2006
—Since shortly after the introduction of the first ICs there has been an effort to put in place standards for IC packages.
Is a standard lead pitch for components possible?
Tuesday, July 3, 2012
—IC packaging technology has led the march of progress since the earliest days of the electronics industry. Decisions made by those responsible for packaging integrated circuits have a ripple effect that extends to the rest of the electronics industry.
3d: Benefits and challenges
Thursday, September 26, 2013
—While a substantial amount of electronic interconnection has been performed in the 3rd dimension throughout the history of electronics, the pursuit of 3D interconnections at chip level is relatively new, even though some prescient inventors in the earliest days of the semiconductor industry foresaw its potential benefit.
Microelectronics Assembly and Packaging (MAP) workshop 2008 review
Monday, February 9, 2009
—The 8th International workshop on microelectronics assembly and
packaging technologies was held in late November of last year and
continues to be one of the best-kept open secrets of the IC packaging
7.8 – IC packaging and interconnection technologies’ 4th dimension challenge
Tuesday, September 4, 2007
—Over the course of the last five or six years there has been an explosion of innovation in the realm of IC packaging.
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TT Electronics’ expertise helps new Audi turbo-diesel and gasoline engines keep cool
Friday, January 30, 2015—Engineers at the company’s Salzburg technical centre created an electrically driven 50-Watt water-pump controller (EWPU) that has been employed in a range of applications including the turbo-intercooler circuit of the advanced EA288 2.0-litre turbo diesel engine. TT Electronics has over 10 years’ experience developing electronic controls for on-demand driven items such as turbo-intercooler pumps and main water pumps up to 600W at 12V and 1,000W for the new 48V on-board supply system.
Engineered Material Systems introduces a new 535-11M-3 UV cure adhesive
Monday, January 26, 2015—Engineered Material Systems, a global supplier of electronic materials for circuit assembly applications, is pleased to debut its 535-11M-3 UV cured epoxy. 535-11M-3 was developed to pass the rigorous reliability requirements in disk drive, camera module, photonics and circuit assembly applications.
Optically clear, low viscosity epoxy features a long open time at room temperature
Monday, January 26, 2015—Master Bond EP62-1LPSP delivers an array of strength, electrical and handling properties that are well suited for bonding, sealing, coating and encapsulation applications. With a tensile lap shear strength exceeding 2,000 psi, it bonds well to a variety of substrates including metals, composites, glass and many plastics.
AI Technology, Inc (AIT) develops ultra-thin die-attach film (DAF) adhesive for new generation of ultra-thin memory stacked chip devices
Friday, January 23, 2015—AI Technology, Inc. (AIT) pioneered the first self-supporting Die-Attach Film (DAF) adhesive for advanced stacked-chip memory packages over 20 years ago. AIT is again revolutionizing wafer level semiconductor packaging by offering Ultra-Thin versions (3-5 microns) of its ESP7660-HK-DAF. Using DAF at the wafer-level has become increasingly prevalent in die-attach for memory modules.
EXTreme Guardian™ power connector system from Molex now available in two-to-six circuit harness assembly options
Thursday, January 22, 2015—Molex Incorporated announces the addition of 2, 3, 4, 5, and 6 circuit harness connector components to its EXTreme Guardian™ Power Connector system. The new components include non-overmolded latching cable receptacle housings, terminal position assurance clips (TPAs), and latchable vertical and right angle headers providing power supply manufactures with more options when designing for the high-current density needs in the computing and telecommunication markets.
The SIPLACE Material Tower optimizes the flow of materials on the production floor
Wednesday, January 21, 2015—With its SIPLACE Material Tower, ASM Assembly System presents its first automated storage system for SMT-specific materials management applications. The climate cabinet, which is available in two sizes, is fully integrated with the SIPLACE Material Manager software. And by interlocking the input and output processes, the SIPLACE Material Manager provides total inventory transparency.
New SMT stencil alloy improves on price and performance
Friday, January 16, 2015—Datum Alloys introduces Tension™, its third generation of stainless steel specifically designed for SMT stencil printing. Datum Tension is hardened to withstand the demands of today’s emerging high tension applications, as well as traditional and frameless mounting. It offers an unprecedented level of value in SMT stencil materials, rivaling the cutting and print performance of FG, Datum’s flagship alloy, and the cost of PhD, Datum’s original specialty stencil alloy.
Meeting the requirements of lead free PCBA testing: Everett Charles Technologies enhances LFRE product line: Lead free long travel probes (LFLT)
Friday, January 9, 2015—Everett Charles Technologies (ECT) extended the probe offerings (LFRE probes) for lead free PCB in-circuit and functional test applications to include long-travel probes (LFLT probes). ECT LFLT probes have almost twice the compliance as standard length probes. The new long-travel probes meet the need for reliable contact solutions for lead free dual-stage in-circuit test fixtures.
Achieve better protection and higher throughput with light-curable conformal coatings
Thursday, December 11, 2014—Dymax Corporation’s new Guide to Light-Cure Conformal Coatings outlines the benefits of using light-cure conformal coatings as well as cost justification, typical processing guidelines and best practices, product selection criteria, data, and industry specifications. Conformal coatings are thin-layer polymers that are applied to the surface of PCBs to protect and electrically insulate the circuit from environmental stresses.
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