Articles & Papers
Pushing the barriers of wafer level device integration
Tuesday, July 8, 2008
—Techsearch has predicted a compound annual growth rate of more than 24% for wafer-level packages between 2005 and 2010. Contract electronics manufacturers and original design manufacturers face a range of handling problems when using these small silicon devices in assemblies.
White paper: Bumping BGAs using solder paste printing process for RFI shields packaging
Friday, January 26, 2007
—One manufacturing process used to attach RFI shields for medical applications/cellular phone circuit board assemblies consists of "snapping" the shell-like shields onto solder spheres that are soldered to printed circuit board [PCB] pads.
7.2 – Evaluation of wafer bumping stencils
Wednesday, March 7, 2007
—In order to better characterize the performance of wafer bumping stencils, a novel solder transfer ratio has been defined that relates the amount of solder paste volume transferred to a wafer to the actual stencil aperture volume.
Cost reduction of wafer level packaging
Monday, August 17, 2009
—Solid state imagers are being incorporated in an ever-expanding diversity of products.
Wafer–level cavity package with via–through pad interconnects
Monday, June 16, 2008
—The continued drive toward solid state imagers with greater pixel numbers and smaller pixels adversely affects yields, particularly through physical contamination during assembly of the camera module.
Metal–based wafer level packaging
Monday, August 17, 2009
—Metal based wafer bonding for WLP has several advantages, including
enhanced hermeticity, and it facilitates vertical integration.
Molded underfill process for the SiP
Friday, January 9, 2009
—For our application and experiment, a new underfilling process, molded underfill (MUF), is being investigated.
Wafer-level solder sphere placement and its implications
Friday, August 6, 2010
—There are three main packaging technologies used by the semiconductor industry today to create solder bumps on wafers: paste printing, electroplating, or sphere dropping.
Integrated testing, modeling and failure analysis of CSPnl for board level reliability
Friday, July 9, 2010
—The wafer level chip scale package (WLCSP) is gaining popularity for its performance and for its ability to meet miniaturization requirements of certain electronic products, especially handheld devices like cell phones.
PACTECH at NEPCON CHINA 2012
Pac Tech - Packaging Technologies is a worldwide leader in both Wafer Level Bumping & Packaging Services and in Advanced Packaging Equipment Manufacturing.
Pac Tech has over 15 years of experience in the industry and has manufacturing sites all around the world, including: Germany, United States, Japan, and Malaysia. These sites can supply both engineering and prototyping services, as well as high volume production.
For more information, please visit: www.pactech.de
Interview: Poornima Shenoy, president of the India Semiconductor Association
Debasish Choudhury interviews Poornima Shenoy, president of the India Semiconductor Association (ISA)
GPD GLOBAL at APEX IPC Expo 2012
GPD demonstrated at the APEX IPC Expo 2012 in San Diego, the PCD and MicroDot technologies on its MAX Series platform. MAX Series dispensing systems offer high accuracy, precision dispensing over a wide range of applications. The MAX Series platforms are ideal for die attach, underfill, MEMS, micro-volume conductive adhesive and paste applications. Max Series equipped with Micro-volume technology enables dispensing for 0201 components as well as die attach adhesives. Further expanding the Max Series capabilities with the continuously volumetric PCD dispense pump yields outstanding results with underfills, encapsulation and LED applications.
For more Information, please visit: www.gpd-global.com
Video Editor: Elisangela Dahlke
Juki at APEX 2009
Juki president Bob Black talks about the new equipment Juki brought to IPC APEX Expo 2009: the JX-100 15,000 pph entry-level placement machine, an upgraded 2080 fine pitch placer, the highest speed soldering machine on the market, and their new flexible, entry-level W510 soldering machine.
Bergen Systems Pvt Ltd at COMPONEX NEPCON India 2009
Pradeep Kaura of Bergen Systems Pvt Ltd introduces a new placement system and in-circuit tester.
MIRTEC at SMT/HYBRID/PACKAGING 2010
David Bennett, managing director of MIRTEC Europe, shows off the MS-11 high speed inline solder paste inspection system and the MV-7XI with the award-winning integrated Intelli-Scan laser inspection system for detecting lifted leads and coplanarity.
Milara at IPC APEX Expo 2011
Stephen Brodeur introduces the fully inline Milara TouchPrint stencil printer series, which is now in full release. It features the fully integrated CyberOptics SE500 post-print inspection technology and Asymtek dot dispensing option.
Nordson Asymtek at IPC APEX Expo 2013
Trevor Galbraith interviews Dan W. Ashley, Market Specialist Printed Circuit Board Assembly of Nordson Asymtek at Apex Expo 2013
Valor at IPC APEX Expo 2010
Julian Coates from the Valor division of Mentor Graphics introduces their complete factory-level control system.
From our Columnists
Wafer level packaging and the third dimension
Tuesday, September 23, 2008
Depending on how liberal one is in their definition of what a wafer
level package is, the technology is either entering its second, third
or perhaps even its fourth or fifth decade of use.
IC packaging technology retrospective
Monday, March 2, 2009
—All IC packaging technology structures since the invention of the
integrated circuit itself have been tasked to perform, at a minimum,
the simple and fundamental tasks of interconnecting and protecting the
semiconductor die and making it useful for interconnection at the next
7.7 – IC packaging
Thursday, August 16, 2007
—While the glamour of the integrated circuit has diminished little over the nearly five decades of its existence, it has become increasingly clear in the last several years that the performance of semiconductor chips is being gated by the IC package.
PiP, PoP and PuP
Monday, April 6, 2009
—Since the beginning, all IC packages have been designed to perform the
basic tasks of interconnecting and protecting the semiconductor die and
making it useful for interconnection at the next level.
6.2 – Standards for IC packages: blessing or burden?
Wednesday, February 1, 2006
—Since shortly after the introduction of the first ICs there has been an effort to put in place standards for IC packages.
Is a standard lead pitch for components possible?
Tuesday, July 3, 2012
—IC packaging technology has led the march of progress since the earliest days of the electronics industry. Decisions made by those responsible for packaging integrated circuits have a ripple effect that extends to the rest of the electronics industry.
3d: Benefits and challenges
Thursday, September 26, 2013
—While a substantial amount of electronic interconnection has been performed in the 3rd dimension throughout the history of electronics, the pursuit of 3D interconnections at chip level is relatively new, even though some prescient inventors in the earliest days of the semiconductor industry foresaw its potential benefit.
Microelectronics Assembly and Packaging (MAP) workshop 2008 review
Monday, February 9, 2009
—The 8th International workshop on microelectronics assembly and
packaging technologies was held in late November of last year and
continues to be one of the best-kept open secrets of the IC packaging
7.8 – IC packaging and interconnection technologies’ 4th dimension challenge
Tuesday, September 4, 2007
—Over the course of the last five or six years there has been an explosion of innovation in the realm of IC packaging.
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Barry Industries introduces 800W termination with 1.12:1 VSWR for basestation, broadcast and radar applications
Tuesday, December 10, 2013—Barry Industries, an ISO9001:2008 certified, ITAR registered manufacturer of high quality thick film resistors, terminations, attenuators and high temperature co-fired ceramic (HTCC) packaging, introduces a RoHS compliant flange mount termination which dissipates 800W with minimal return loss over a DC to 1GHz bandwidth.
Accelerate firmware development time for Linear Technology ICs with the Linduino platform
Wednesday, December 4, 2013—Linear Technology Corporation announces the Linduino™ One development tool, an Arduino-compatible platform for developing and distributing firmware libraries and code for Linear Technology’s SPI and I²C-compatible integrated circuits. The Linduino One board interfaces to more than 300 QuikEval™ demonstration cards, supporting a variety of product types including analog-to-digital converters (ADCs), digital-to-analog converters (DACs), power monitors, intelligent Hot Swap™ controllers, temperature sensors, LED drivers, and battery management systems.
EV Group introduces full-field UV nanoimprint lithography system For photonics, LED and BioMEMS production
Wednesday, December 4, 2013—EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today introduced the EVG®720 automated UV nanoimprint lithography (UV-NIL) system. Providing full-field imprint lithography with an integrated soft stamp/template fabrication capability, the EVG720 system enables throughputs of more than 60 wafers per hour with the lowest cost of ownership (CoO).
Laird expands EMI shielding portfolio with edge guide clip-on Strip
Monday, December 2, 2013—Laird, a global technology company and an industry leader in high-performance and cost-effective EMI Management solutions, announced the release of a new Fingerstock product, the Edge Guide Clip-on Strip. Ideal for virtually every application where Printed Circuit Boards (PCBs) need to be grounded and/or shielded, this new product reduces installation and labor costs and is available in custom lengths.
Bourns announces new low profile TVS diode
Thursday, November 28, 2013—Bourns, Inc., a manufacturer and supplier of electronic components, announced the availability of its new low profile transient voltage suppressor (TVS) diode, designated Bourns® Model CDDFN2-T3.3B. Bourns designed its new low capacitance (13 pF) diode in a smaller surface mount package as an optimal ESD, EFT and surge protection solution. The new TVS diode provides reliable circuit protection for external ports in a broad range of electronic devices such as computers and peripherals, communication systems, cellular phones, handheld portable electronics and audio and video equipment.
New module kit for parallel test and programming in gang applications
Thursday, November 28, 2013—GOEPEL electronic has extended its SCANFLEX® Boundary Scan hardware product range, now introducing the SFX Gang Test Module Kit as a new solution for parallel test and programming of up to 32 different assemblies with an integrated Mass Interconnect Interface from Virginia Panel. The kit, consisting of three basic modules, is an easy-to-integrate complete solution for parallel applications based on Embedded System Access (ESA) technologies providing throughput increase by factors of 16 or 32.
New Gore® Polyvent Compact Series vent delivers higher performance in a smaller-footprint for automotive electronic housings
Wednesday, November 27, 2013—With its new GORE® PolyVent Compact Series, W. L. Gore & Associates, Inc. introduces higher-performance venting in a smaller footprint for automotive electronic housings. About 30% smaller than the widely-used PolyVent Snap-Fit product family, the new GORE® PolyVent Compact Series is easier to integrate into even the smallest housings. It provides a higher level of protection for sensitive components like sensors, motors and control units, while providing reliable and rapid pressure equalization.
Innovative sensors require advanced test equipment
Monday, November 25, 2013—Multitest, a designer and manufacturer of final test handlers, contactors and load boards used by integrated device manufacturers (IDMs) and final test subcontractors worldwide, announces that its leading solution for 3-axis magnetometer plus 2-axis low g-test and calibration fully supports the technical features of today’s advanced 3D hall sensors. The modular concept for sensor test equipment ensures the most economic equipment utilization.
Toughened two component epoxy is optically clear and resists thermal cycling
Monday, November 25, 2013—Master Bond EP38CL was developed for bonding, sealing, coating and encapsulation applications that require toughness and durability. With a Shore D hardness exceeding 75, its toughness is a unique property that imparts resistance to rigorous thermal cycling, impact and mechanical shock.
Section coming soon!