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Articles & Papers
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Pushing the barriers of wafer level device integration
Tuesday, July 8, 2008— Techsearch has predicted a compound annual growth rate of more than 24% for wafer-level packages between 2005 and 2010. Contract electronics manufacturers and original design manufacturers face a range of handling problems when using these small silicon devices in assemblies.
White paper: Bumping BGAs using solder paste printing process for RFI shields packaging
Friday, January 26, 2007— One manufacturing process used to attach RFI shields for medical applications/cellular phone circuit board assemblies consists of "snapping" the shell-like shields onto solder spheres that are soldered to printed circuit board [PCB] pads.
7.2 – Evaluation of wafer bumping stencils
Wednesday, March 7, 2007— In order to better characterize the performance of wafer bumping stencils, a novel solder transfer ratio has been defined that relates the amount of solder paste volume transferred to a wafer to the actual stencil aperture volume.
Cost reduction of wafer level packaging
Monday, August 17, 2009— Solid state imagers are being incorporated in an ever-expanding diversity of products.
Wafer–level cavity package with via–through pad interconnects
Monday, June 16, 2008— The continued drive toward solid state imagers with greater pixel numbers and smaller pixels adversely affects yields, particularly through physical contamination during assembly of the camera module.
Metal–based wafer level packaging
Monday, August 17, 2009— Metal based wafer bonding for WLP has several advantages, including
enhanced hermeticity, and it facilitates vertical integration.
Molded underfill process for the SiP
Friday, January 9, 2009— For our application and experiment, a new underfilling process, molded underfill (MUF), is being investigated.
Wafer-level solder sphere placement and its implications
Friday, August 6, 2010— There are three main packaging technologies used by the semiconductor industry today to create solder bumps on wafers: paste printing, electroplating, or sphere dropping.
Integrated testing, modeling and failure analysis of CSPnl for board level reliability
Friday, July 9, 2010— The wafer level chip scale package (WLCSP) is gaining popularity for its performance and for its ability to meet miniaturization requirements of certain electronic products, especially handheld devices like cell phones.
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Videos
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PACTECH at NEPCON CHINA 2012
Pac Tech - Packaging Technologies is a worldwide leader in both Wafer Level Bumping & Packaging Services and in Advanced Packaging Equipment Manufacturing.
Pac Tech has over 15 years of experience in the industry and has manufacturing sites all around the world, including: Germany, United States, Japan, and Malaysia. These sites can supply both engineering and prototyping services, as well as high volume production.
For more information, please visit: www.pactech.de
Interview: Poornima Shenoy, president of the India Semiconductor Association
Debasish Choudhury interviews Poornima Shenoy, president of the India Semiconductor Association (ISA)
GPD GLOBAL at APEX IPC Expo 2012
GPD demonstrated at the APEX IPC Expo 2012 in San Diego, the PCD and MicroDot technologies on its MAX Series platform. MAX Series dispensing systems offer high accuracy, precision dispensing over a wide range of applications. The MAX Series platforms are ideal for die attach, underfill, MEMS, micro-volume conductive adhesive and paste applications. Max Series equipped with Micro-volume technology enables dispensing for 0201 components as well as die attach adhesives. Further expanding the Max Series capabilities with the continuously volumetric PCD dispense pump yields outstanding results with underfills, encapsulation and LED applications.
For more Information, please visit: www.gpd-global.com
Video Editor: Elisangela Dahlke
Juki at APEX 2009
Juki president Bob Black talks about the new equipment Juki brought to IPC APEX Expo 2009: the JX-100 15,000 pph entry-level placement machine, an upgraded 2080 fine pitch placer, the highest speed soldering machine on the market, and their new flexible, entry-level W510 soldering machine.
Bergen Systems Pvt Ltd at COMPONEX NEPCON India 2009
Pradeep Kaura of Bergen Systems Pvt Ltd introduces a new placement system and in-circuit tester.
MIRTEC at SMT/HYBRID/PACKAGING 2010
David Bennett, managing director of MIRTEC Europe, shows off the MS-11 high speed inline solder paste inspection system and the MV-7XI with the award-winning integrated Intelli-Scan laser inspection system for detecting lifted leads and coplanarity.
Milara at IPC APEX Expo 2011
Stephen Brodeur introduces the fully inline Milara TouchPrint stencil printer series, which is now in full release. It features the fully integrated CyberOptics SE500 post-print inspection technology and Asymtek dot dispensing option.
Nordson Asymtek at IPC APEX Expo 2013
Trevor Galbraith interviews Dan W. Ashley, Market Specialist Printed Circuit Board Assembly of Nordson Asymtek at Apex Expo 2013
Valor at IPC APEX Expo 2010
Julian Coates from the Valor division of Mentor Graphics introduces their complete factory-level control system.
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From our Columnists
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Wafer level packaging and the third dimension
Tuesday, September 23, 2008— Depending on how liberal one is in their definition of what a wafer
level package is, the technology is either entering its second, third
or perhaps even its fourth or fifth decade of use.
IC packaging technology retrospective
Monday, March 2, 2009— All IC packaging technology structures since the invention of the
integrated circuit itself have been tasked to perform, at a minimum,
the simple and fundamental tasks of interconnecting and protecting the
semiconductor die and making it useful for interconnection at the next
level.
7.7 – IC packaging
Thursday, August 16, 2007— While the glamour of the integrated circuit has diminished little over the nearly five decades of its existence, it has become increasingly clear in the last several years that the performance of semiconductor chips is being gated by the IC package.
PiP, PoP and PuP
Monday, April 6, 2009— Since the beginning, all IC packages have been designed to perform the
basic tasks of interconnecting and protecting the semiconductor die and
making it useful for interconnection at the next level.
6.2 – Standards for IC packages: blessing or burden?
Wednesday, February 1, 2006— Since shortly after the introduction of the first ICs there has been an effort to put in place standards for IC packages.
Is a standard lead pitch for components possible?
Tuesday, July 3, 2012— IC packaging technology has led the march of progress since the earliest days of the electronics industry. Decisions made by those responsible for packaging integrated circuits have a ripple effect that extends to the rest of the electronics industry.
Microelectronics Assembly and Packaging (MAP) workshop 2008 review
Monday, February 9, 2009— The 8th International workshop on microelectronics assembly and
packaging technologies was held in late November of last year and
continues to be one of the best-kept open secrets of the IC packaging
industry.
7.8 – IC packaging and interconnection technologies’ 4th dimension challenge
Tuesday, September 4, 2007— Over the course of the last five or six years there has been an explosion of innovation in the realm of IC packaging.
IC packaging technology retrospective
Friday, May 8, 2009— Part one left off noting that surface mount brought with it significant
advantages to IC packaging but also that there was need to provide
guidance for future development. The result of that effort is something
that is now known as the
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Latest SMT Answers questions
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There are no questions related to this area at this time. Visit the SMT Answers section to ask your own or explore questions from other process areas and topics. |
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Latest Products
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DKN Research co-develops thin metal-free flexible circuits with micro via holes for scientific and medical devices
Thursday, May 9, 2013—DKN Research, a leading engineering firm specializing in microelectronics and packaging technology, now carries thin metal-free flexible circuits with reliable via holes. The Haverhill Massachusetts based firm developed a series of processing technologies to generate thin graphite traces on both sides of thin polyimide film specifically targeting those scientific and medical applications that require the elimination of metals that have large atomic numbers and weights from electronic devices.
Rutronik presents the i.MX6 based industrial CPU module from emtrion
Tuesday, May 7, 2013—emtrion extends its DIMM family by the new industrial processor module DIMM-MX6, which is based on the multicore Cortex-A9 i.MX6 SoC family from Freescale. The module offers a full electrical and mechanical compatibility with the other modules of the emtrion DIMM series. It is available at the distributor Rutronik as of now.
The i.MX6 processor from Freescale brings high computing capabilities with up to 10.000 DMIPS, multiple NEON and VPFU co-processors at a low power level, without requiring any active cooling system. This module is ideal for industrial applications as well as multimedia applications using its powerful GPU.
Hesse Mechatronics launches heavy wire and ribbon bonding services for early stage product development
Monday, May 6, 2013—Hesse Mechatronics, Inc. (formerly Hesse & Knipps), the Americas subsidiary of Hesse GmbH, leading manufacturer of high-speed fine pitch wedge bonders and fully automatic heavy wire and ribbon bonders for the backend semiconductor industry, announces that it will offer application development, prototyping and pre-production services on a newly installed BONDJET BJ939 Fully Automatic Heavy Wire Bonder at the company’s west coast demonstration and applications lab, located at long-time company manufacturer’s representative Chalman Technologies in Anaheim, California.
Rudolph receives customer acceptance of first JetStep system for advanced packaging applications
Friday, May 3, 2013—
Rudolph Technologies, Inc. (NASDAQ: RTEC), a leading provider of process characterization, photolithography equipment and software for the semiconductor, FPD, LED and solar industries, announced that the first of its new JetStep™ Photolithographic Systems has been accepted and sold to a leading provider of advanced semiconductor packaging and test services. The system is being used for wafer level packaging processes where its flexible substrate handling and unique optical capabilities deliver valuable benefits.
Rudolph Technologies launches S3000SX transparent thin film metrology system for 28nm node and below
Friday, May 3, 2013—Rudolph Technologies, Inc. (NASDAQ: RTEC), a leading provider of process characterization, photolithography equipment and software for the semiconductor, FPD, LED and solar industries, announced today the release of the S3000SX™ thin film metrology system for transparent films in advanced semiconductor fabrication applications at the 28nm node and below.
Double shoulder contact and movable ground pin QFP test & burn-in socket
Thursday, May 2, 2013—Among such high density packages, the QFP has proven to be the right choice when it comes to combine high functional integration with excellent connection reliability. With its gull-wing shaped lead feet surface mount, QFP is most tolerant towards vibration, flexing, warping and other stress applied to the PCB. This mechanical reliability has been the reason why QFP is the first choice for industries that are operating in harsh conditions such as automotive.
Multitest ecoAmp™: Kelvin contactor for high-power applications proves performance
Thursday, May 2, 2013—Multitest, a designer and manufacturer of final test handlers, contactors and load boards used by integrated device manufacturers (IDMs) and final test subcontractors worldwide, announces that its ecoAmp™ high-power Kelvin contactor successfully passed a challenging evaluation for an automotive application at an European-based IDM. The patent pending ecoAmp™ is a state-of-the-art solution for high-power applications of 1000+ amperes.
Two component room temperature curing epoxy meets UL 94V-0 specifications for flame retardancy
Wednesday, May 1, 2013—Featuring a non-halogen filler, Master Bond EP21FRNS-2 passes UL 94V-0 testing for flame retardancy in potting, encapsulation and casting applications. It produces very low smoke levels and is well suited for the computer, aerospace and related industries.
MARTIN Introduces IR temperature measurement sensors for ENHANCED rework
Wednesday, April 24, 2013—The IR sensor is installed at the Advanced Vision Placement unit, next to the camera. The sensor module has a laser pointer integrated to indicate the area of measurement on the PCB surface. The sensor mount is easy to unlock and allows the user to swipe the measurement location over the PCB easily. Advantages include ease of use as a monitoring sensor (no need for capton tape), stable and reliable measurement, and for use in preheat and/or closed-loop operations.
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Manufacturers
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Section coming soon!
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Industry News
