Articles & Papers
Pushing the barriers of wafer level device integration
Tuesday, July 8, 2008
—Techsearch has predicted a compound annual growth rate of more than 24% for wafer-level packages between 2005 and 2010. Contract electronics manufacturers and original design manufacturers face a range of handling problems when using these small silicon devices in assemblies.
White paper: Bumping BGAs using solder paste printing process for RFI shields packaging
Friday, January 26, 2007
—One manufacturing process used to attach RFI shields for medical applications/cellular phone circuit board assemblies consists of "snapping" the shell-like shields onto solder spheres that are soldered to printed circuit board [PCB] pads.
7.2 – Evaluation of wafer bumping stencils
Wednesday, March 7, 2007
—In order to better characterize the performance of wafer bumping stencils, a novel solder transfer ratio has been defined that relates the amount of solder paste volume transferred to a wafer to the actual stencil aperture volume.
Cost reduction of wafer level packaging
Monday, August 17, 2009
—Solid state imagers are being incorporated in an ever-expanding diversity of products.
Wafer–level cavity package with via–through pad interconnects
Monday, June 16, 2008
—The continued drive toward solid state imagers with greater pixel numbers and smaller pixels adversely affects yields, particularly through physical contamination during assembly of the camera module.
Metal–based wafer level packaging
Monday, August 17, 2009
—Metal based wafer bonding for WLP has several advantages, including
enhanced hermeticity, and it facilitates vertical integration.
Molded underfill process for the SiP
Friday, January 9, 2009
—For our application and experiment, a new underfilling process, molded underfill (MUF), is being investigated.
Wafer-level solder sphere placement and its implications
Friday, August 6, 2010
—There are three main packaging technologies used by the semiconductor industry today to create solder bumps on wafers: paste printing, electroplating, or sphere dropping.
Integrated testing, modeling and failure analysis of CSPnl for board level reliability
Friday, July 9, 2010
—The wafer level chip scale package (WLCSP) is gaining popularity for its performance and for its ability to meet miniaturization requirements of certain electronic products, especially handheld devices like cell phones.
PACTECH at NEPCON CHINA 2012
Pac Tech - Packaging Technologies is a worldwide leader in both Wafer Level Bumping & Packaging Services and in Advanced Packaging Equipment Manufacturing.
Pac Tech has over 15 years of experience in the industry and has manufacturing sites all around the world, including: Germany, United States, Japan, and Malaysia. These sites can supply both engineering and prototyping services, as well as high volume production.
For more information, please visit: www.pactech.de
Interview: Poornima Shenoy, president of the India Semiconductor Association
Debasish Choudhury interviews Poornima Shenoy, president of the India Semiconductor Association (ISA)
GPD GLOBAL at APEX IPC Expo 2012
GPD demonstrated at the APEX IPC Expo 2012 in San Diego, the PCD and MicroDot technologies on its MAX Series platform. MAX Series dispensing systems offer high accuracy, precision dispensing over a wide range of applications. The MAX Series platforms are ideal for die attach, underfill, MEMS, micro-volume conductive adhesive and paste applications. Max Series equipped with Micro-volume technology enables dispensing for 0201 components as well as die attach adhesives. Further expanding the Max Series capabilities with the continuously volumetric PCD dispense pump yields outstanding results with underfills, encapsulation and LED applications.
For more Information, please visit: www.gpd-global.com
Video Editor: Elisangela Dahlke
Juki at APEX 2009
Juki president Bob Black talks about the new equipment Juki brought to IPC APEX Expo 2009: the JX-100 15,000 pph entry-level placement machine, an upgraded 2080 fine pitch placer, the highest speed soldering machine on the market, and their new flexible, entry-level W510 soldering machine.
Bergen Systems Pvt Ltd at COMPONEX NEPCON India 2009
Pradeep Kaura of Bergen Systems Pvt Ltd introduces a new placement system and in-circuit tester.
MIRTEC at SMT/HYBRID/PACKAGING 2010
David Bennett, managing director of MIRTEC Europe, shows off the MS-11 high speed inline solder paste inspection system and the MV-7XI with the award-winning integrated Intelli-Scan laser inspection system for detecting lifted leads and coplanarity.
Milara at IPC APEX Expo 2011
Stephen Brodeur introduces the fully inline Milara TouchPrint stencil printer series, which is now in full release. It features the fully integrated CyberOptics SE500 post-print inspection technology and Asymtek dot dispensing option.
Nordson Asymtek at IPC APEX Expo 2013
Trevor Galbraith interviews Dan W. Ashley, Market Specialist Printed Circuit Board Assembly of Nordson Asymtek at Apex Expo 2013
Valor at IPC APEX Expo 2010
Julian Coates from the Valor division of Mentor Graphics introduces their complete factory-level control system.
From our Columnists
Wafer level packaging and the third dimension
Tuesday, September 23, 2008
Depending on how liberal one is in their definition of what a wafer
level package is, the technology is either entering its second, third
or perhaps even its fourth or fifth decade of use.
IC packaging technology retrospective
Monday, March 2, 2009
—All IC packaging technology structures since the invention of the
integrated circuit itself have been tasked to perform, at a minimum,
the simple and fundamental tasks of interconnecting and protecting the
semiconductor die and making it useful for interconnection at the next
7.7 – IC packaging
Thursday, August 16, 2007
—While the glamour of the integrated circuit has diminished little over the nearly five decades of its existence, it has become increasingly clear in the last several years that the performance of semiconductor chips is being gated by the IC package.
PiP, PoP and PuP
Monday, April 6, 2009
—Since the beginning, all IC packages have been designed to perform the
basic tasks of interconnecting and protecting the semiconductor die and
making it useful for interconnection at the next level.
6.2 – Standards for IC packages: blessing or burden?
Wednesday, February 1, 2006
—Since shortly after the introduction of the first ICs there has been an effort to put in place standards for IC packages.
Is a standard lead pitch for components possible?
Tuesday, July 3, 2012
—IC packaging technology has led the march of progress since the earliest days of the electronics industry. Decisions made by those responsible for packaging integrated circuits have a ripple effect that extends to the rest of the electronics industry.
3d: Benefits and challenges
Thursday, September 26, 2013
—While a substantial amount of electronic interconnection has been performed in the 3rd dimension throughout the history of electronics, the pursuit of 3D interconnections at chip level is relatively new, even though some prescient inventors in the earliest days of the semiconductor industry foresaw its potential benefit.
Microelectronics Assembly and Packaging (MAP) workshop 2008 review
Monday, February 9, 2009
—The 8th International workshop on microelectronics assembly and
packaging technologies was held in late November of last year and
continues to be one of the best-kept open secrets of the IC packaging
7.8 – IC packaging and interconnection technologies’ 4th dimension challenge
Tuesday, September 4, 2007
—Over the course of the last five or six years there has been an explosion of innovation in the realm of IC packaging.
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Pulse Electronics introduces new ultra-low profile offset and halogen free 10GBASE-T RJ45 integrated connector module
Thursday, March 13, 2014—Pulse Electronics Corporation (NYSE: PULS), a provider of electronic components, introduces the JT3-1101HL ultra-low profile offset and halogen free 10GBASE-T (10 Gbit/s Ethernet over unshielded twisted-pair) RJ45 integrated connector module (ICM) for server, router, and storage applications. Pulse's 10G RJ45 ICM is only 9.04mm tall once installed on the PCB. This gives flexibility to 10GBASE-T hardware designers who have an I/O panel with limited height, but who need to configure it so the RJ45 is in line with the PCB.
Tektronix unveils 40 Gb/s high-performance BERT for Datacom & long haul testing
Tuesday, March 11, 2014—Tektronix, Inc., a worldwide provider of test, measurement and monitoring instrumentation, unveiled the industry's first fully integrated 40 Gb/s Programmable Pattern Generator (PPG). This 40 Gb/s PPG, along with the previously announced 40 Gb/s Programmable Error Detector now comprise a complete 40 Gb/s BERT solution. With 200 fs Random Jitter (RJ) and 8 ps risetime performance, the new Tektronix PPG4001 delivers the performance and signal quality critical for serial data testing at 40 Gb/s.
SCHOTT’s high-tech electronic packages enable maximum speed data transfer in high-frequency applications
Tuesday, March 11, 2014—The international technology Group SCHOTT enables the development of very fast, next-generation Ethernet transceivers by offering hermetic packages with miniaturized high-temperature co-fired ceramics (HTCC) feedthroughs for 100 Gbit/s Quad Small Form-factor Pluggable (QSFP) transceivers, one of the fastest data communication transceivers on the market.
New Vishay Intertechnology 4 A synchronous buck regulator offers switching frequencies to 1.5 MHz and 95 % efficiency
Monday, March 10, 2014—Vishay Intertechnology, Inc. (NYSE: VSH) expanded its microBUCK® family of integrated synchronous buck regulators with a new 4 A device offering high programmable switching frequencies of up to 1.5 MHz and a wide input voltage range of 4.5 V to 15 V. The Vishay Siliconix SiP12109 features integrated high- and low-side power MOSFETs in the space-saving 3 mm by 3 mm QFN-16 package, providing designers with a complete high-current solution in only 180 mm².
Vishay Intertechnology releases two new matched pairs of AEC-Q101-qualified, high-speed IR emitters/photodiodes
Thursday, March 6, 2014—Vishay Intertechnology, Inc. (NYSE: VSH) introduced two new matched pairs of AEC-Q101-qualified, high-speed 940 nm infrared (IR) emitters and silicon PIN photodiodes in compact 3 mm by 2 mm side-view surface-mount packages. For automotive and consumer IR touch panels, the VSMB10940X01/VEMD10940FX01 feature a profile of 1 mm while the VSMB11940X01/VEMD11940FX01 offer a profile of 0.6 mm, the industry's lowest for side-looking, AEC-Q101-qualified components. All Vishay Semiconductors devices released offer an ultra-wide ± 75° angle of half-intensity.
Vishay Intertechnology releases first AEC-Q101-qualified MOSFETs to feature ThunderFET® technology
Wednesday, March 5, 2014—Vishay Intertechnology, Inc. (NYSE: VSH) released the first AEC-Q101-qualified TrenchFET® power MOSFETs to feature ThunderFET® technology. To increase efficiency and save space in automotive applications, the Vishay Siliconix 100 V n-channel SQJ402EP, SQJ488EP, and SQD50N10-8m9L offer some of the lowest on-resistance values available in the PowerPAK® SO-8L and DPAK packages.
Low noise bias generator in 2mm x 2mm DFN
Wednesday, March 5, 2014—Linear Technology Corporation announces the LT3048, a step-up DC/DC converter with an integrated LDO output that delivers a low noise, low ripple 15V bias supply. The LT3048-15 delivers up to 40mA of continuous output current at 15V with output ripple and noise less than 500µVPK-PK and 0.1% load regulation. The device operates from an input voltage range of 2.7V to 4.8V, making it suitable for single-cell Li-Ion batteries or 3.3V logic rails.
EM Microelectronic announces first secure ISO/IEC15693 compliant IC for anti-counterfeiting and authenticity safeguarding of goods
Tuesday, March 4, 2014—EM Microelectronic, the semiconductor company of the Swatch Group and a world-leading supplier for RFID and NFC circuits, announced the EM4237, the first high-secure ISO/IEC15693 compliant device offering unequalled RF performances and enabling efficient and secure solutions for anti-counterfeiting and brand protection. The EM4237 provides a universal identity card and an encrypted tamperproof digital certificate to convey the guarantee of good quality anywhere in the world.
SUSS MicroTec launches DSC300 Gen2: Next generation projection scanner for advanced packaging
Tuesday, March 4, 2014—SUSS MicroTec, a global supplier of equipment and process solutions for the semiconductor industry and related markets, has launched the DSC300 Gen2 projection scanner. SUSS MicroTec's DSC300 platform for wafer sizes up to 300 mm is based on the projection lithography technology developed by SUSS MicroTec Photonic Systems Inc. (formerly Tamarack Scientific).
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