Articles & Papers
Pushing the barriers of wafer level device integration
Tuesday, July 8, 2008
—Techsearch has predicted a compound annual growth rate of more than 24% for wafer-level packages between 2005 and 2010. Contract electronics manufacturers and original design manufacturers face a range of handling problems when using these small silicon devices in assemblies.
White paper: Bumping BGAs using solder paste printing process for RFI shields packaging
Friday, January 26, 2007
—One manufacturing process used to attach RFI shields for medical applications/cellular phone circuit board assemblies consists of "snapping" the shell-like shields onto solder spheres that are soldered to printed circuit board [PCB] pads.
7.2 – Evaluation of wafer bumping stencils
Wednesday, March 7, 2007
—In order to better characterize the performance of wafer bumping stencils, a novel solder transfer ratio has been defined that relates the amount of solder paste volume transferred to a wafer to the actual stencil aperture volume.
Cost reduction of wafer level packaging
Monday, August 17, 2009
—Solid state imagers are being incorporated in an ever-expanding diversity of products.
Wafer–level cavity package with via–through pad interconnects
Monday, June 16, 2008
—The continued drive toward solid state imagers with greater pixel numbers and smaller pixels adversely affects yields, particularly through physical contamination during assembly of the camera module.
Metal–based wafer level packaging
Monday, August 17, 2009
—Metal based wafer bonding for WLP has several advantages, including
enhanced hermeticity, and it facilitates vertical integration.
Molded underfill process for the SiP
Friday, January 9, 2009
—For our application and experiment, a new underfilling process, molded underfill (MUF), is being investigated.
Wafer-level solder sphere placement and its implications
Friday, August 6, 2010
—There are three main packaging technologies used by the semiconductor industry today to create solder bumps on wafers: paste printing, electroplating, or sphere dropping.
Integrated testing, modeling and failure analysis of CSPnl for board level reliability
Friday, July 9, 2010
—The wafer level chip scale package (WLCSP) is gaining popularity for its performance and for its ability to meet miniaturization requirements of certain electronic products, especially handheld devices like cell phones.
PACTECH at NEPCON CHINA 2012
Pac Tech - Packaging Technologies is a worldwide leader in both Wafer Level Bumping & Packaging Services and in Advanced Packaging Equipment Manufacturing.
Pac Tech has over 15 years of experience in the industry and has manufacturing sites all around the world, including: Germany, United States, Japan, and Malaysia. These sites can supply both engineering and prototyping services, as well as high volume production.
For more information, please visit: www.pactech.de
Interview: Poornima Shenoy, president of the India Semiconductor Association
Debasish Choudhury interviews Poornima Shenoy, president of the India Semiconductor Association (ISA)
GPD GLOBAL at APEX IPC Expo 2012
GPD demonstrated at the APEX IPC Expo 2012 in San Diego, the PCD and MicroDot technologies on its MAX Series platform. MAX Series dispensing systems offer high accuracy, precision dispensing over a wide range of applications. The MAX Series platforms are ideal for die attach, underfill, MEMS, micro-volume conductive adhesive and paste applications. Max Series equipped with Micro-volume technology enables dispensing for 0201 components as well as die attach adhesives. Further expanding the Max Series capabilities with the continuously volumetric PCD dispense pump yields outstanding results with underfills, encapsulation and LED applications.
For more Information, please visit: www.gpd-global.com
Video Editor: Elisangela Dahlke
Juki at APEX 2009
Juki president Bob Black talks about the new equipment Juki brought to IPC APEX Expo 2009: the JX-100 15,000 pph entry-level placement machine, an upgraded 2080 fine pitch placer, the highest speed soldering machine on the market, and their new flexible, entry-level W510 soldering machine.
Bergen Systems Pvt Ltd at COMPONEX NEPCON India 2009
Pradeep Kaura of Bergen Systems Pvt Ltd introduces a new placement system and in-circuit tester.
OKI at NEPCON South China 2014
We congratulate OK International's Paul Wood at Nepcon South China for winning an award for their latest solder cleaning solution 'Solder Bee' and discusses how OKI respond to the rapid advances in new packages launched onto the market.
MIRTEC at SMT/HYBRID/PACKAGING 2010
David Bennett, managing director of MIRTEC Europe, shows off the MS-11 high speed inline solder paste inspection system and the MV-7XI with the award-winning integrated Intelli-Scan laser inspection system for detecting lifted leads and coplanarity.
Milara at IPC APEX Expo 2011
Stephen Brodeur introduces the fully inline Milara TouchPrint stencil printer series, which is now in full release. It features the fully integrated CyberOptics SE500 post-print inspection technology and Asymtek dot dispensing option.
Nordson Asymtek at IPC APEX Expo 2013
Trevor Galbraith interviews Dan W. Ashley, Market Specialist Printed Circuit Board Assembly of Nordson Asymtek at Apex Expo 2013
From our Columnists
Wafer level packaging and the third dimension
Tuesday, September 23, 2008
Depending on how liberal one is in their definition of what a wafer
level package is, the technology is either entering its second, third
or perhaps even its fourth or fifth decade of use.
IC packaging technology retrospective
Monday, March 2, 2009
—All IC packaging technology structures since the invention of the
integrated circuit itself have been tasked to perform, at a minimum,
the simple and fundamental tasks of interconnecting and protecting the
semiconductor die and making it useful for interconnection at the next
7.7 – IC packaging
Thursday, August 16, 2007
—While the glamour of the integrated circuit has diminished little over the nearly five decades of its existence, it has become increasingly clear in the last several years that the performance of semiconductor chips is being gated by the IC package.
PiP, PoP and PuP
Monday, April 6, 2009
—Since the beginning, all IC packages have been designed to perform the
basic tasks of interconnecting and protecting the semiconductor die and
making it useful for interconnection at the next level.
6.2 – Standards for IC packages: blessing or burden?
Wednesday, February 1, 2006
—Since shortly after the introduction of the first ICs there has been an effort to put in place standards for IC packages.
Is a standard lead pitch for components possible?
Tuesday, July 3, 2012
—IC packaging technology has led the march of progress since the earliest days of the electronics industry. Decisions made by those responsible for packaging integrated circuits have a ripple effect that extends to the rest of the electronics industry.
3d: Benefits and challenges
Thursday, September 26, 2013
—While a substantial amount of electronic interconnection has been performed in the 3rd dimension throughout the history of electronics, the pursuit of 3D interconnections at chip level is relatively new, even though some prescient inventors in the earliest days of the semiconductor industry foresaw its potential benefit.
Microelectronics Assembly and Packaging (MAP) workshop 2008 review
Monday, February 9, 2009
—The 8th International workshop on microelectronics assembly and
packaging technologies was held in late November of last year and
continues to be one of the best-kept open secrets of the IC packaging
7.8 – IC packaging and interconnection technologies’ 4th dimension challenge
Tuesday, September 4, 2007
—Over the course of the last five or six years there has been an explosion of innovation in the realm of IC packaging.
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Multitest’s MEMS and sensor test and calibration portfolio supports the increasing functionalities of mobile phones
Friday, November 21, 2014—The Multitest has been providing MEMS and sensor test and calibration equipment for more than ten years. Originally driven by the automotive market Multitest continuously expanded the product offering to meet the needs of consumer and mobility applications. Today Multitest provides solutions for accelerometers, gyroscopes, pressure and gas sensors, humidity sensors, magnetometers, microphones, optical sensors and oscillators. The set-ups cover test of singulated packages, high-parallel testing up to multi-DOF test.
USI releases new precision metering pump for conformal coating PMP 100/200 for prism system
Wednesday, November 19, 2014—Ultrasonic Systems, Inc. (USI), a manufacturer of high-performance ultrasonic spray coating equipment for electronics assembly, medical, fuel cell, semiconductor and solar applications announces the release of the Precision Metering Pump (PMP) for conformal coating applications. The PMP overcomes the limitations of traditional pressurized liquid delivery systems associated with liquid viscosity changes due to changing ambient conditions.
Koh Young Technology launches KSMART integrated technology solution
Tuesday, November 18, 2014—Koh Young Technology announces the debut of the KSMART Integrated Technology Solution, a comprehensive productivity and process control center. The success of KSMART implementation results from the convergence of new Koh Young software technologies working in concert with 3D AOI and SPI capabilities. These technologies include the KSMART Remote Monitoring System (RMS), KSMART Link, and others, which will be added to KSMART as they are developed.
Nordson DAGE announces further orders for its unique patented hot pin pull test method on the 4000Plus Bondtester
Tuesday, November 18, 2014—Nordson DAGE, a division of Nordson Corporation (NASDAQ: NDSN), reports that several leading manufacturers of complex multilayer printed circuit boards (PCBs) have adopted the company’s hot pin pull test method for checking the integrity of solder ball attach on packages and PCBs in accordance with the industry standard IPC9708. This particular standard provides guidelines for bond testing to identify potential pad craters.
NASA low outgassing approved, one component epoxy features a glass transition temperature of 225°C
Monday, November 17, 2014—Formulated to operate over the wide temperature range of -80°F to +650°F, Master Bond EP17HT-LO is a one part epoxy for bonding, sealing, coating and encapsulation applications. This low viscosity system has very low exotherm upon curing and can be cast in sections up to and beyond a ½ inch in thickness. As a single component system, it offers convenient handling, doesn’t require mixing and has an unlimited working life at room temperature.
Hamamatsu introduces radiation line sensor for non-invasive inspection of pipe wall thinning in industrial plants
Monday, November 17, 2014—Hamamatsu Photonics K.K. has developed an energy-discriminating radiation line sensor (part number: C13247), which features a direct conversion type semiconductor, to inspect pipe wall thinning due to corrosion. The product will be available from 1st December 2014 to companies that provide inspection services to facilities such as petroleum refineries, petrochemical plants, and power plants.
Combined test technologies for Altera SoC solutions
Monday, November 17, 2014—GOEPEL electronics announces the availability of VarioTAP® and ChipVORX® models for Altera® System-on-Chip (SoC) solutions at Electronica in Munich. Chips of this type combine the FPGA logic with a so-called Hard Processor System (HPS) in a single package. Using the Goepel VarioTAP® and ChipVORX® models, allows the integrated processors as well as the FPGA logic to become embedded instruments for test and programming of the solutions they are fitted to.
PARMI and Aegis develop xLink machine adapter to connect SPI data to FactoryLogix manufacturing software in real-time
Monday, November 17, 2014—PARMI, a leader in 3-D solder paste inspection (SPI) of printed circuit boards (PCBs), together with Aegis Software, announces the development of the xLink adapter to enable real-time connectivity of SPI results to Aegis’ FactoryLogix Manufacturing Operations Systems. With real-time data integration, manufacturers immediately can identify SPI defects and take corrective actions to improve PCB yield.
Innovative adhesive thermal laminate from Bergquist solves CTE-mismatch challenges
Wednesday, November 12, 2014—Bond-Ply LMS-HD consists of a thermally conductive low-modulus silicone compound coated on a cured core, and double lined with protective films. This design effectively absorbs mechanical stresses induced by assembly-level CTE mismatch, or by shock and vibration. Two thickness grades give designers a choice of 0.254mm or 0.305mm thicknesses for structurally adhering discrete semiconductors such as power components, or PCBs, to a heat sink.
Section coming soon!