Articles & Papers
Pushing the barriers of wafer level device integration
Tuesday, July 8, 2008
—Techsearch has predicted a compound annual growth rate of more than 24% for wafer-level packages between 2005 and 2010. Contract electronics manufacturers and original design manufacturers face a range of handling problems when using these small silicon devices in assemblies.
White paper: Bumping BGAs using solder paste printing process for RFI shields packaging
Friday, January 26, 2007
—One manufacturing process used to attach RFI shields for medical applications/cellular phone circuit board assemblies consists of "snapping" the shell-like shields onto solder spheres that are soldered to printed circuit board [PCB] pads.
7.2 – Evaluation of wafer bumping stencils
Wednesday, March 7, 2007
—In order to better characterize the performance of wafer bumping stencils, a novel solder transfer ratio has been defined that relates the amount of solder paste volume transferred to a wafer to the actual stencil aperture volume.
Cost reduction of wafer level packaging
Monday, August 17, 2009
—Solid state imagers are being incorporated in an ever-expanding diversity of products.
Wafer–level cavity package with via–through pad interconnects
Monday, June 16, 2008
—The continued drive toward solid state imagers with greater pixel numbers and smaller pixels adversely affects yields, particularly through physical contamination during assembly of the camera module.
Metal–based wafer level packaging
Monday, August 17, 2009
—Metal based wafer bonding for WLP has several advantages, including
enhanced hermeticity, and it facilitates vertical integration.
Molded underfill process for the SiP
Friday, January 9, 2009
—For our application and experiment, a new underfilling process, molded underfill (MUF), is being investigated.
Wafer-level solder sphere placement and its implications
Friday, August 6, 2010
—There are three main packaging technologies used by the semiconductor industry today to create solder bumps on wafers: paste printing, electroplating, or sphere dropping.
Integrated testing, modeling and failure analysis of CSPnl for board level reliability
Friday, July 9, 2010
—The wafer level chip scale package (WLCSP) is gaining popularity for its performance and for its ability to meet miniaturization requirements of certain electronic products, especially handheld devices like cell phones.
PACTECH at NEPCON CHINA 2012
Pac Tech - Packaging Technologies is a worldwide leader in both Wafer Level Bumping & Packaging Services and in Advanced Packaging Equipment Manufacturing.
Pac Tech has over 15 years of experience in the industry and has manufacturing sites all around the world, including: Germany, United States, Japan, and Malaysia. These sites can supply both engineering and prototyping services, as well as high volume production.
For more information, please visit: www.pactech.de
Interview: Poornima Shenoy, president of the India Semiconductor Association
Debasish Choudhury interviews Poornima Shenoy, president of the India Semiconductor Association (ISA)
GPD GLOBAL at APEX IPC Expo 2012
GPD demonstrated at the APEX IPC Expo 2012 in San Diego, the PCD and MicroDot technologies on its MAX Series platform. MAX Series dispensing systems offer high accuracy, precision dispensing over a wide range of applications. The MAX Series platforms are ideal for die attach, underfill, MEMS, micro-volume conductive adhesive and paste applications. Max Series equipped with Micro-volume technology enables dispensing for 0201 components as well as die attach adhesives. Further expanding the Max Series capabilities with the continuously volumetric PCD dispense pump yields outstanding results with underfills, encapsulation and LED applications.
For more Information, please visit: www.gpd-global.com
Video Editor: Elisangela Dahlke
Juki at APEX 2009
Juki president Bob Black talks about the new equipment Juki brought to IPC APEX Expo 2009: the JX-100 15,000 pph entry-level placement machine, an upgraded 2080 fine pitch placer, the highest speed soldering machine on the market, and their new flexible, entry-level W510 soldering machine.
OKI at NEPCON South China 2014
We congratulate OK International's Paul Wood at Nepcon South China for winning an award for their latest solder cleaning solution 'Solder Bee' and discusses how OKI respond to the rapid advances in new packages launched onto the market.
Bergen Systems Pvt Ltd at COMPONEX NEPCON India 2009
Pradeep Kaura of Bergen Systems Pvt Ltd introduces a new placement system and in-circuit tester.
MIRTEC at SMT/HYBRID/PACKAGING 2010
David Bennett, managing director of MIRTEC Europe, shows off the MS-11 high speed inline solder paste inspection system and the MV-7XI with the award-winning integrated Intelli-Scan laser inspection system for detecting lifted leads and coplanarity.
Milara at IPC APEX Expo 2011
Stephen Brodeur introduces the fully inline Milara TouchPrint stencil printer series, which is now in full release. It features the fully integrated CyberOptics SE500 post-print inspection technology and Asymtek dot dispensing option.
Nordson Asymtek at IPC APEX Expo 2013
Trevor Galbraith interviews Dan W. Ashley, Market Specialist Printed Circuit Board Assembly of Nordson Asymtek at Apex Expo 2013
From our Columnists
Wafer level packaging and the third dimension
Tuesday, September 23, 2008
Depending on how liberal one is in their definition of what a wafer
level package is, the technology is either entering its second, third
or perhaps even its fourth or fifth decade of use.
IC packaging technology retrospective
Monday, March 2, 2009
—All IC packaging technology structures since the invention of the
integrated circuit itself have been tasked to perform, at a minimum,
the simple and fundamental tasks of interconnecting and protecting the
semiconductor die and making it useful for interconnection at the next
7.7 – IC packaging
Thursday, August 16, 2007
—While the glamour of the integrated circuit has diminished little over the nearly five decades of its existence, it has become increasingly clear in the last several years that the performance of semiconductor chips is being gated by the IC package.
PiP, PoP and PuP
Monday, April 6, 2009
—Since the beginning, all IC packages have been designed to perform the
basic tasks of interconnecting and protecting the semiconductor die and
making it useful for interconnection at the next level.
6.2 – Standards for IC packages: blessing or burden?
Wednesday, February 1, 2006
—Since shortly after the introduction of the first ICs there has been an effort to put in place standards for IC packages.
Is a standard lead pitch for components possible?
Tuesday, July 3, 2012
—IC packaging technology has led the march of progress since the earliest days of the electronics industry. Decisions made by those responsible for packaging integrated circuits have a ripple effect that extends to the rest of the electronics industry.
3d: Benefits and challenges
Thursday, September 26, 2013
—While a substantial amount of electronic interconnection has been performed in the 3rd dimension throughout the history of electronics, the pursuit of 3D interconnections at chip level is relatively new, even though some prescient inventors in the earliest days of the semiconductor industry foresaw its potential benefit.
Microelectronics Assembly and Packaging (MAP) workshop 2008 review
Monday, February 9, 2009
—The 8th International workshop on microelectronics assembly and
packaging technologies was held in late November of last year and
continues to be one of the best-kept open secrets of the IC packaging
7.8 – IC packaging and interconnection technologies’ 4th dimension challenge
Tuesday, September 4, 2007
—Over the course of the last five or six years there has been an explosion of innovation in the realm of IC packaging.
Latest SMT Answers questions
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Thermally conductive, two component epoxy passes USP Class VI tests and ISO 10993-5 specifications
Thursday, September 18, 2014—With biocompatibility and cytotoxicity certifications, Master Bond EP21AOLV-2Med is often selected for bonding, sealing, coating and encapsulation applications in the medical device industry. This two component epoxy system withstands a variety of sterilization methods, including EtO, radiation and many cold sterilants.
Protecting sensor electronics from the elements
Tuesday, September 16, 2014—The sensor's electronics, in the form of a small printed circuit board (PCB) contained within the unit, had not only to be protected from adverse atmospheric conditions, but also meet certain requirements posed by the hazardous nature of the sensor location. Based on these operating conditions, Electrolube was tasked with selecting an appropriate resin for the PCB.
Vishay Intertechnology automotive-grade PIN photodiodes deliver high reverse light current to 9.5 µA
Friday, September 12, 2014—Vishay Intertechnology, Inc. (NYSE: VSH) is broadening its optoelectronics portfolio with the introduction of two new automotive-grade high-speed silicon PIN photodiodes in clear- and black-epoxy 1206 surface-mount packages measuring 4 mm by 2 mm by 1.05 mm.
Microscan launches verification monitoring interface (VMI) to grade barcodes and monitor trends in quality in real time
Thursday, September 11, 2014—Microscan, a global technology leader in barcode, machine vision, and lighting solutions, announces the availability of the Verification Monitoring Interface (VMI), a new software solution specially engineered for monitoring the quality of barcodes as they are produced on parts, labels, and packaging.
A 25X microscope that fits right in your pocket from CircuitMedic
Wednesday, September 10, 2014—The 25X Measuring Microscope Pen from CircuitMedic is a powerful pocket sized microscope with measuring reticle for precision measurements.
This pen is ideal for inspecting defects and measuring conductor and pad widths, plated holes, and other tiny features and components on circuit boards.
Magnetic sensor calibration & test: Highly integrated solutions substantially reduces cost
Tuesday, September 9, 2014—Multitest’s sensor calibration and test equipment for magnetic sensors using Helmholtz coils provide a highly integrated and compact solution for volume test. The setup ideally combines the advantages of Multitest’s modular concept for sensor test equipment with the benefits of a compact and robust design. This way low investment cost and highest ease-of-use on the test floor are ensured.
Everett Charles Technologies releases HyperCore™ material to full ZIP™ probe product line
Wednesday, September 3, 2014—Everett Charles Technologies (ECT) releases the HyperCore™ material to the full ZIP™ product line. ZIP™ is an ECT single probe family that is dedicated to semiconductor test applications. HyperCore™ is an innovative, non-plated and homogenous probe material optimized for longer probe life, longer cleaning cycles and reliable contact.
PARMI announces new SPI defect repair feature for SIGMA X
Friday, August 29, 2014—PARMI, a leader in 3-D solder paste inspection (SPI) of printed circuit boards announces the Jet Solder Jet Dispenser Unit for its award-winning SIGMA X SPI Series. Jet repairs solder paste deposits within the machine to eliminate expensive rework and scrap, maximizes throughput and increases ROI.
New Vishay intertechnology 3 A synchronous buck regulator delivers design simplicity and space savings
Wednesday, August 27, 2014—Vishay Intertechnology, Inc. (NYSE: VSH) expanded its microBUCK® family of integrated synchronous buck regulators with a new 3 A device offering a fixed 650 kHz switching frequency and a wide input voltage range of 4.5 V to 15 V. The Vishay Siliconix SiP12116 combines high-side and low-side n-channel MOSFETs with current-mode, constant on-time (CM-COT) control in the space-saving 3 mm by 3 mm DFN10 package with thermal pad, providing designers with a complete buck regulator design in only 100 mm².
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