Articles & Papers
Pushing the barriers of wafer level device integration
Tuesday, July 8, 2008
—Techsearch has predicted a compound annual growth rate of more than 24% for wafer-level packages between 2005 and 2010. Contract electronics manufacturers and original design manufacturers face a range of handling problems when using these small silicon devices in assemblies.
White paper: Bumping BGAs using solder paste printing process for RFI shields packaging
Friday, January 26, 2007
—One manufacturing process used to attach RFI shields for medical applications/cellular phone circuit board assemblies consists of "snapping" the shell-like shields onto solder spheres that are soldered to printed circuit board [PCB] pads.
7.2 – Evaluation of wafer bumping stencils
Wednesday, March 7, 2007
—In order to better characterize the performance of wafer bumping stencils, a novel solder transfer ratio has been defined that relates the amount of solder paste volume transferred to a wafer to the actual stencil aperture volume.
Cost reduction of wafer level packaging
Monday, August 17, 2009
—Solid state imagers are being incorporated in an ever-expanding diversity of products.
Wafer–level cavity package with via–through pad interconnects
Monday, June 16, 2008
—The continued drive toward solid state imagers with greater pixel numbers and smaller pixels adversely affects yields, particularly through physical contamination during assembly of the camera module.
Metal–based wafer level packaging
Monday, August 17, 2009
—Metal based wafer bonding for WLP has several advantages, including
enhanced hermeticity, and it facilitates vertical integration.
Molded underfill process for the SiP
Friday, January 9, 2009
—For our application and experiment, a new underfilling process, molded underfill (MUF), is being investigated.
Wafer-level solder sphere placement and its implications
Friday, August 6, 2010
—There are three main packaging technologies used by the semiconductor industry today to create solder bumps on wafers: paste printing, electroplating, or sphere dropping.
Integrated testing, modeling and failure analysis of CSPnl for board level reliability
Friday, July 9, 2010
—The wafer level chip scale package (WLCSP) is gaining popularity for its performance and for its ability to meet miniaturization requirements of certain electronic products, especially handheld devices like cell phones.
PACTECH at NEPCON CHINA 2012
Pac Tech - Packaging Technologies is a worldwide leader in both Wafer Level Bumping & Packaging Services and in Advanced Packaging Equipment Manufacturing.
Pac Tech has over 15 years of experience in the industry and has manufacturing sites all around the world, including: Germany, United States, Japan, and Malaysia. These sites can supply both engineering and prototyping services, as well as high volume production.
For more information, please visit: www.pactech.de
Interview: Poornima Shenoy, president of the India Semiconductor Association
Debasish Choudhury interviews Poornima Shenoy, president of the India Semiconductor Association (ISA)
GPD GLOBAL at APEX IPC Expo 2012
GPD demonstrated at the APEX IPC Expo 2012 in San Diego, the PCD and MicroDot technologies on its MAX Series platform. MAX Series dispensing systems offer high accuracy, precision dispensing over a wide range of applications. The MAX Series platforms are ideal for die attach, underfill, MEMS, micro-volume conductive adhesive and paste applications. Max Series equipped with Micro-volume technology enables dispensing for 0201 components as well as die attach adhesives. Further expanding the Max Series capabilities with the continuously volumetric PCD dispense pump yields outstanding results with underfills, encapsulation and LED applications.
For more Information, please visit: www.gpd-global.com
Video Editor: Elisangela Dahlke
Juki at APEX 2009
Juki president Bob Black talks about the new equipment Juki brought to IPC APEX Expo 2009: the JX-100 15,000 pph entry-level placement machine, an upgraded 2080 fine pitch placer, the highest speed soldering machine on the market, and their new flexible, entry-level W510 soldering machine.
Bergen Systems Pvt Ltd at COMPONEX NEPCON India 2009
Pradeep Kaura of Bergen Systems Pvt Ltd introduces a new placement system and in-circuit tester.
MIRTEC at SMT/HYBRID/PACKAGING 2010
David Bennett, managing director of MIRTEC Europe, shows off the MS-11 high speed inline solder paste inspection system and the MV-7XI with the award-winning integrated Intelli-Scan laser inspection system for detecting lifted leads and coplanarity.
Milara at IPC APEX Expo 2011
Stephen Brodeur introduces the fully inline Milara TouchPrint stencil printer series, which is now in full release. It features the fully integrated CyberOptics SE500 post-print inspection technology and Asymtek dot dispensing option.
Nordson Asymtek at IPC APEX Expo 2013
Trevor Galbraith interviews Dan W. Ashley, Market Specialist Printed Circuit Board Assembly of Nordson Asymtek at Apex Expo 2013
Valor at IPC APEX Expo 2010
Julian Coates from the Valor division of Mentor Graphics introduces their complete factory-level control system.
From our Columnists
Wafer level packaging and the third dimension
Tuesday, September 23, 2008
Depending on how liberal one is in their definition of what a wafer
level package is, the technology is either entering its second, third
or perhaps even its fourth or fifth decade of use.
IC packaging technology retrospective
Monday, March 2, 2009
—All IC packaging technology structures since the invention of the
integrated circuit itself have been tasked to perform, at a minimum,
the simple and fundamental tasks of interconnecting and protecting the
semiconductor die and making it useful for interconnection at the next
7.7 – IC packaging
Thursday, August 16, 2007
—While the glamour of the integrated circuit has diminished little over the nearly five decades of its existence, it has become increasingly clear in the last several years that the performance of semiconductor chips is being gated by the IC package.
PiP, PoP and PuP
Monday, April 6, 2009
—Since the beginning, all IC packages have been designed to perform the
basic tasks of interconnecting and protecting the semiconductor die and
making it useful for interconnection at the next level.
6.2 – Standards for IC packages: blessing or burden?
Wednesday, February 1, 2006
—Since shortly after the introduction of the first ICs there has been an effort to put in place standards for IC packages.
Is a standard lead pitch for components possible?
Tuesday, July 3, 2012
—IC packaging technology has led the march of progress since the earliest days of the electronics industry. Decisions made by those responsible for packaging integrated circuits have a ripple effect that extends to the rest of the electronics industry.
3d: Benefits and challenges
Thursday, September 26, 2013
—While a substantial amount of electronic interconnection has been performed in the 3rd dimension throughout the history of electronics, the pursuit of 3D interconnections at chip level is relatively new, even though some prescient inventors in the earliest days of the semiconductor industry foresaw its potential benefit.
Microelectronics Assembly and Packaging (MAP) workshop 2008 review
Monday, February 9, 2009
—The 8th International workshop on microelectronics assembly and
packaging technologies was held in late November of last year and
continues to be one of the best-kept open secrets of the IC packaging
7.8 – IC packaging and interconnection technologies’ 4th dimension challenge
Tuesday, September 4, 2007
—Over the course of the last five or six years there has been an explosion of innovation in the realm of IC packaging.
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Intel Ships more than five million chipset devices to Rochester Electronics
Wednesday, July 30, 2014—Rochester Electronics recently increased its inventory of Intel product by more than five million devices following a massive transfer of chipset products. As an authorized distributor for mature and EOL products from the semiconductor giant, Rochester will continue to support Intel customers with ongoing demand for more than 60 unique part types which make up this most recent shipment.
Cogiscan’s new Genealogy Module provides complete traceability
Monday, July 28, 2014—Cogiscan Inc., Track, Trace and Control (TTC) solutions provider for the electronics manufacturing industry, is pleased to introduce a new Genealogy Module. This module offers the capability to continue the tracking, traceability and control of Printed Circuit Board Assemblies (PCBAs) throughout subsequent assembly levels, all the way to the finished product.
Viscom introduces the new software release SI 7.47
Wednesday, July 23, 2014—Viscom is pleased to introduce Software Release SI 7.47. With this new Release, Viscom introduces numerous innovations and improvements in the area of inspection plan generation and analysis software for its inspection systems. The highlights of Release 7.47 can be clearly seen: advancements in the downlink function for Solder Paste Inspection (SPI), the automation of the popular Integrated Verification, as well as the new µBGA analysis and the new XM converter, are genuine performance enhancements.
Vishay Intertechnology's new series of precision thin film chip resistor arrays features gold terminations for conductive gluing, with relative tolerance down to ±0.05 %, and relative TCR down to ±5 ppm/K
Wednesday, July 23, 2014—Vishay Intertechnology, Inc. (NYSE: VSH) has introduced a new series of precision thin film chip resistor arrays featuring gold terminations for conductive gluing. Offering two integrated resistors on one substrate, the ACAS 0606 ATAU resistor array combines high-temperature operation to 155 °C with relative tolerance down to ±0.05 % and relative TCR down to ±5 ppm/K.
Intersil announces highly accurate digital power monitor capable of industry’s widest common mode input voltage range
Monday, July 21, 2014—Intersil Corporation (NASDAQ: ISIL), a provider of innovative power management and precision analog solutions, today announced the ISL2802x family of digital power monitors capable of supporting a wide common mode input voltage range of 0V to 60V. The ISL2802x family is comprised of three devices offering a range of capability including full featured bi-directional, high-side and low-side digital current sense and voltage monitors with a serial interface with a high level of integration.
Electrolube improve operator safety with Isocyanate-Free Resin
Thursday, July 17, 2014—Electrolube, the global manufacturer at the forefront of electro-chemicals technology, has developed a clear polyester resin that delivers the high performance of a polyurethane resin without the use of hazardous isocyanates. The flexible encapsulation resin, PE7500, completely eliminates any health risk from isocyanate exposure, proven to cause irritation to the eyes, skin and respiratory system.
Power device evaluation at temperature with integrated hot plate
Thursday, July 17, 2014—The integration of a temperature controlled thermal platform with the Agilent B1506A Power Device Analyzer has been introduced by inTEST Thermal Solutions and Agilent. The newly designed hot plate permits automated control of platform temperature, from enclosure ambient to 250°C, for characterization of power devices such as IGBTs and MOSFETs.
VarioTAP® processor emulation for Texas Instruments AM355x family
Friday, July 11, 2014—GOEPEL electronic extends the VarioTAP® technology for universal processor emulation for the Texas Instruments AM355x family of the Sitara™ series. The processor is reconfigured to provide design-integrated test and programming instruments via the native debug port. A respective VarioTAP® model, as part of an extensive IP library, contains all relevant access information for the respective target processor.
SUSS MicroTec launches ELD 300 Excimer laser debonder for 3D-integration
Tuesday, July 8, 2014—The laser debonder can be used as a stand-alone, semi-automated system or as an integrated process module in SUSS MicroTec’s XBC300 Gen2 platform. The debonding method used in the ELD300 relies on a 308nm Excimer laser to separate the glass carrier from a tape mounted thin wafer. The ultraviolet light of the pulsed laser beam is absorbed in the adhesive or in an optional UV absorption layer within a few hundred nanometers.
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