Articles & Papers
Pushing the barriers of wafer level device integration
Tuesday, July 8, 2008
—Techsearch has predicted a compound annual growth rate of more than 24% for wafer-level packages between 2005 and 2010. Contract electronics manufacturers and original design manufacturers face a range of handling problems when using these small silicon devices in assemblies.
White paper: Bumping BGAs using solder paste printing process for RFI shields packaging
Friday, January 26, 2007
—One manufacturing process used to attach RFI shields for medical applications/cellular phone circuit board assemblies consists of "snapping" the shell-like shields onto solder spheres that are soldered to printed circuit board [PCB] pads.
7.2 – Evaluation of wafer bumping stencils
Wednesday, March 7, 2007
—In order to better characterize the performance of wafer bumping stencils, a novel solder transfer ratio has been defined that relates the amount of solder paste volume transferred to a wafer to the actual stencil aperture volume.
Cost reduction of wafer level packaging
Monday, August 17, 2009
—Solid state imagers are being incorporated in an ever-expanding diversity of products.
Wafer–level cavity package with via–through pad interconnects
Monday, June 16, 2008
—The continued drive toward solid state imagers with greater pixel numbers and smaller pixels adversely affects yields, particularly through physical contamination during assembly of the camera module.
Metal–based wafer level packaging
Monday, August 17, 2009
—Metal based wafer bonding for WLP has several advantages, including
enhanced hermeticity, and it facilitates vertical integration.
Molded underfill process for the SiP
Friday, January 9, 2009
—For our application and experiment, a new underfilling process, molded underfill (MUF), is being investigated.
Wafer-level solder sphere placement and its implications
Friday, August 6, 2010
—There are three main packaging technologies used by the semiconductor industry today to create solder bumps on wafers: paste printing, electroplating, or sphere dropping.
Integrated testing, modeling and failure analysis of CSPnl for board level reliability
Friday, July 9, 2010
—The wafer level chip scale package (WLCSP) is gaining popularity for its performance and for its ability to meet miniaturization requirements of certain electronic products, especially handheld devices like cell phones.
PACTECH at NEPCON CHINA 2012
Pac Tech - Packaging Technologies is a worldwide leader in both Wafer Level Bumping & Packaging Services and in Advanced Packaging Equipment Manufacturing.
Pac Tech has over 15 years of experience in the industry and has manufacturing sites all around the world, including: Germany, United States, Japan, and Malaysia. These sites can supply both engineering and prototyping services, as well as high volume production.
For more information, please visit: www.pactech.de
Interview: Poornima Shenoy, president of the India Semiconductor Association
Debasish Choudhury interviews Poornima Shenoy, president of the India Semiconductor Association (ISA)
GPD GLOBAL at APEX IPC Expo 2012
GPD demonstrated at the APEX IPC Expo 2012 in San Diego, the PCD and MicroDot technologies on its MAX Series platform. MAX Series dispensing systems offer high accuracy, precision dispensing over a wide range of applications. The MAX Series platforms are ideal for die attach, underfill, MEMS, micro-volume conductive adhesive and paste applications. Max Series equipped with Micro-volume technology enables dispensing for 0201 components as well as die attach adhesives. Further expanding the Max Series capabilities with the continuously volumetric PCD dispense pump yields outstanding results with underfills, encapsulation and LED applications.
For more Information, please visit: www.gpd-global.com
Video Editor: Elisangela Dahlke
Juki at APEX 2009
Juki president Bob Black talks about the new equipment Juki brought to IPC APEX Expo 2009: the JX-100 15,000 pph entry-level placement machine, an upgraded 2080 fine pitch placer, the highest speed soldering machine on the market, and their new flexible, entry-level W510 soldering machine.
Bergen Systems Pvt Ltd at COMPONEX NEPCON India 2009
Pradeep Kaura of Bergen Systems Pvt Ltd introduces a new placement system and in-circuit tester.
MIRTEC at SMT/HYBRID/PACKAGING 2010
David Bennett, managing director of MIRTEC Europe, shows off the MS-11 high speed inline solder paste inspection system and the MV-7XI with the award-winning integrated Intelli-Scan laser inspection system for detecting lifted leads and coplanarity.
OKI at NEPCON South China 2014
We congratulate OK International's Paul Wood at Nepcon South China for winning an award for their latest solder cleaning solution 'Solder Bee' and discusses how OKI respond to the rapid advances in new packages launched onto the market.
Milara at IPC APEX Expo 2011
Stephen Brodeur introduces the fully inline Milara TouchPrint stencil printer series, which is now in full release. It features the fully integrated CyberOptics SE500 post-print inspection technology and Asymtek dot dispensing option.
Nordson Asymtek at IPC APEX Expo 2013
Trevor Galbraith interviews Dan W. Ashley, Market Specialist Printed Circuit Board Assembly of Nordson Asymtek at Apex Expo 2013
From our Columnists
Wafer level packaging and the third dimension
Tuesday, September 23, 2008
Depending on how liberal one is in their definition of what a wafer
level package is, the technology is either entering its second, third
or perhaps even its fourth or fifth decade of use.
IC packaging technology retrospective
Monday, March 2, 2009
—All IC packaging technology structures since the invention of the
integrated circuit itself have been tasked to perform, at a minimum,
the simple and fundamental tasks of interconnecting and protecting the
semiconductor die and making it useful for interconnection at the next
7.7 – IC packaging
Thursday, August 16, 2007
—While the glamour of the integrated circuit has diminished little over the nearly five decades of its existence, it has become increasingly clear in the last several years that the performance of semiconductor chips is being gated by the IC package.
PiP, PoP and PuP
Monday, April 6, 2009
—Since the beginning, all IC packages have been designed to perform the
basic tasks of interconnecting and protecting the semiconductor die and
making it useful for interconnection at the next level.
6.2 – Standards for IC packages: blessing or burden?
Wednesday, February 1, 2006
—Since shortly after the introduction of the first ICs there has been an effort to put in place standards for IC packages.
Is a standard lead pitch for components possible?
Tuesday, July 3, 2012
—IC packaging technology has led the march of progress since the earliest days of the electronics industry. Decisions made by those responsible for packaging integrated circuits have a ripple effect that extends to the rest of the electronics industry.
3d: Benefits and challenges
Thursday, September 26, 2013
—While a substantial amount of electronic interconnection has been performed in the 3rd dimension throughout the history of electronics, the pursuit of 3D interconnections at chip level is relatively new, even though some prescient inventors in the earliest days of the semiconductor industry foresaw its potential benefit.
Microelectronics Assembly and Packaging (MAP) workshop 2008 review
Monday, February 9, 2009
—The 8th International workshop on microelectronics assembly and
packaging technologies was held in late November of last year and
continues to be one of the best-kept open secrets of the IC packaging
7.8 – IC packaging and interconnection technologies’ 4th dimension challenge
Tuesday, September 4, 2007
—Over the course of the last five or six years there has been an explosion of innovation in the realm of IC packaging.
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GOEPEL electronics introduces new test strategy for IoT devices
Wednesday, May 27, 2015—JEDOS represents by its architecture a complete operating system that uses the natively integrated processor to execute embedded diagnostic functional tests in real time. It is loaded and controlled via JTAG, or alternative debug interfaces, directly into the processor so the user does not require native firmware.
Altium adds new extension to flagship PCB design tool for seamless SOLIDWORKS(r) collaboration
Friday, May 22, 2015—Altium Limited, has released a new extension for Altium Designer that provides integrated design data and a managed design revision environment between electrical design teams in Altium Designer and mechanical design teams in SOLIDWORKS(r).
Alltemated Inc. announces new versions of PLACE-N-BONDTM underfilms for BGA reliability enhancement
Wednesday, May 20, 2015—Alltemated, Inc. announced that PLACE-N-BOND products will now be offered with glue dots pre-applied to the strip as an alternative for “tacky-pads.” Testing is now even more attractive as it seamlessly integrates into a standard SMT feeder and saves the time and expense of having to modify circuit boards to accommodate PLACE-N-BOND during trials.
GE’s phoenix x|aminer inspection system now available with CMOS flat panel detector-based computed tomography
Friday, May 1, 2015—GE (NYSE:GE) Measurement & Control, a division of GE Oil & Gas, introduced the CMOS-flat panel detector version of the 5-axis phoenix x|aminer. With computed tomography (CT) capability and a CT-dedicated software package, the latest version generates extremely high quality imaging for 3D and 2D inspection in the electronics sector. The new functionality saves time and costs in failure analysis, process control in printed circuit board assemblies and component inspection, and in research and development.
Engineered Material Systems introduces new 535-11M-7 UV cure adhesive
Friday, April 24, 2015—Engineered Material Systems, a global supplier of electronic materials for circuit assembly applications, is pleased to debut its 535-11M-7 UV cured epoxy. 535-11M-7 was developed to pass the rigorous reliability requirements in disk drive, camera module, photonics and circuit assembly applications.
Indium Corporation releases BiAgX® solder paste technology as drop-in replacement for high-Pb solders
Tuesday, March 31, 2015—Environmental and legislative concerns are driving consumers away from products using solders that contain lead (Pb), including solders used in die-attach applications for analog semiconductor assembly. Indium Corporation’s BiAgX® solder paste technology is a high-melting, lead-free (Pb-free) solder paste technology that serves as a drop-in replacement for the high-Pb solders used in many high-reliability die-attach and electronics assembly applications.
Testing and programming of ultra-low power processors
Monday, March 30, 2015—The processor is reconfigured to provide design-integrated test and programming instruments via the SWD port. The user can select the corresponding processor to test and validate the connected hardware as well as program Flash memories.
Mentor Graphics launches Xpedition Package Integrator flow for IC package-board design
Tuesday, March 24, 2015—Mentor Graphics Corporation (NASDAQ: MENT) announced its new Xpedition® Package Integrator flow, the industry’s broadest solution for integrated circuit (IC), package, and printed circuit board (PCB) co-design and optimization. The Package Integrator solution automates planning, assembly and optimization of today’s complex multi-die packages.
Mentor Graphics announces HyperLynx Tool for power-aware signal integrity simulation
Monday, March 16, 2015—Mentor Graphics Corporation (NASDAQ: MENT) announced its newest version of the HyperLynx® Signal Integrity/Power Integrity (SI/PI) product for high-speed printed circuit board (PCB) designs. The HyperLynx product addresses high-speed systems design problems throughout the design flow—starting at the earliest architectural stages through post-layout verification.
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