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  • Equipment manufacturers resume discussions on FOPLP with TSMC as the lead

    Image courtesy of TrendForce.

    Source: DigiTimes (Image courtesy of TrendForce)

    As Apple prepares to launch its first AI smartphone in September, the third quarter is expected to see a surge in stocking demand. This has not only pushed TSMC’s market value to new highs but also sparked widespread discussions about AI chip-related supply chains and ongoing R&D technologies.

    TSMC’s order book is full, with customers rushing for CoWoS (Chip on Wafer on Substrate) capacity. NVIDIA and AMD, driven by high demand for AI GPUs, are using advanced packaging to enhance computing power for cloud computing, big data analysis, AI training, and inference, primarily focusing on CoWoS. However, the industry believes that high-end smartphones and autonomous driving fields also require advanced packaging, though no alternatives have emerged yet.

    The Rise of Fan-Out Panel Level Packaging (FOPLP)

    Recently, AI chip manufacturers have been actively engaging with TSMC and Taiwanese OSAT (Outsourced Semiconductor Assembly and Test) giants to discuss using panel and Fan-Out Panel Level Packaging (FOPLP) technologies for chip packaging.

    Equipment manufacturers involved with TSMC have indicated that TSMC discussed FOPLP prospects with them several years ago, but the trend was not mature enough then, and technical issues such as panel warpage control remained unresolved. With AI demand surpassing market expectations in the past year or two, discussions have resumed, with industry insiders noting that “2024 will see a relatively higher seriousness towards FOPLP.”

    FOPLP is not a new technology. Six years ago, academia and industry mentioned that by replacing “round” with “square,” FOPLP offers 84% higher area utilization compared to Fan-Out Wafer Level Packaging (FOWLP), enabling the production of larger, more efficient, and cost-effective components. Both area and efficiency are superior to the current mainstream FOWLP, signaling a potential shift from FOWLP to FOPLP.

    However, FOPLP has not become mainstream due to challenges in cost, yield, and inconsistent specifications. For AI GPUs, high prices and technical maturity are still being enhanced. NVIDIA and AMD have approached TSMC to discuss this technology, hoping to spur Taiwanese OSAT firms to accelerate FOPLP development. Industry insiders suggest that TSMC’s use of FOPLP technology for chip packaging may not be realized until 2025-2026.

    Currently, FOPLP line width and spacing cannot match FOWLP levels, limiting its applications to mature processes such as Power Management ICs (PMICs) and other cost-sensitive products. Once the technology matures, it will be introduced into mainstream consumer IC products.

    Industry Players and Applications

    TSMC, Amkor, ASE, and Siliconware are the main participants in FOWLP technology, while Samsung Electronics, ASE, and Powertech are the promoters of FOPLP technology. Samsung developed FOPLP technology for its Samsung Watch series eight years ago and began mass production in 2018. The Galaxy Watch 6 chips still use this technology, integrating CPU, PMIC, and DRAM into a chipset using FOPLP combined with Package on Package (PoP) technology.

    The supply chain reports that Google Pixel 7 and Pixel 7 Pro application processors (APs) use FOPLP technology for packaging. However, some industry insiders believe that FOPLP is challenging for high-end smartphone chips due to cost and yield issues.

    Impact on OSAT Industry and Future Outlook

    FOPLP technology impacts the OSAT industry development in two ways: it enables OSAT firms to increase their market share in consumer ICs and enter multi-chip packaging and heterogeneous integration businesses, which are future trends. Additionally, once mature, GPU manufacturers can expand the packaging size of AI GPUs, creating a win-win scenario.

    In conclusion, CoWoS will remain irreplaceable in the high-performance computing field for the next 3-5 years, with leading-edge 3D packaging SoIC gaining prominence in high-end applications. For OSAT firms, the greatest advantage lies in achieving large volumes and product upgrades while maintaining cost-effectiveness.

    The future of FOPLP as the next-generation advanced packaging tool depends on chip manufacturers’ product positioning, resolution of yield issues caused by warpage, and the overall performance and cost output to determine if it offers value for customers.

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