Source: Ki-ill Moon, Head of PKG Technology Development, SK hynix (first published in EE Times)
Intel co-founder Gordon Moore famously predicted that the number of transistors on a chip would double every one to two years. Known as Moore’s Law, this forecast held true until recently thanks to developments in pattern-miniaturization technology. However, Moore’s Law may no longer be valid as technological advancements have reached their limits and costs have risen from the use of expensive equipment such as extreme ultraviolet (EUV) lithography systems. Meanwhile, there is still great market demand for ever-improving semiconductor technologies. To bridge this gap in technological advancement and meet the semiconductor market’s needs, one solution has emerged: advanced semiconductor packaging technology.
Although advanced packaging is highly complex and involves a wide mixture of technologies, interconnection technology remains at its core. This article will cover how packaging technology has evolved and SK hynix’s recent efforts and accomplishments in helping to advance the field.
The importance of interconnection in advanced packaging
First, it is important to note that interconnection technology is a critical and necessary part of packaging. Chips are interconnected through packaging to receive power, exchange signals, and, ultimately, operate. As the speed, density, and functions of a semiconductor product change depending on how the interconnection is made, interconnection methods are constantly changing and developing.
In addition to developing various processes to realize fine patterns in fabs, there have been comprehensive efforts to advance interconnection techniques in the packaging process. As a result, the following four types of interconnection techniques have been developed: wire bonding, flip-chip bonding, through-silicon via1 (TSV) bonding, and hybrid bonding with chiplets.2
1Through-silicon via (TSV): A type of vertical interconnect access (via) that completely passes through a silicon die or wafer to enable the stacking of silicon dice.
2Chiplet: Technology that divides chips by use such as controller or high-speed memory and manufactures them as separate wafers before re-connecting them in the packaging process.
3Hybrid bonding has not been applied to the above products. Specifications are an estimate.
Wire bonding
Wire bonding is the first interconnection method that was developed. Typically, materials with good electrical properties such as gold, silver, and copper are used as wires to bond chips and substrates. This is the most cost-effective and reliable interconnection method, but due to its long electrical path, it is not suitable for newer devices that require high-speed operations. As a result, this method is being adopted for mobile DRAM and NAND chips used in mobile devices that do not require rapid operations.
Flip-chip bonding
Flip-chip bonding overcomes the shortcomings of wire bonding. The length of its electrical path is several tenths of that found in wire bonding, making it suitable for high-speed operations. Processed at the wafer level, flip-chip bonding also offers superior productivity compared to wire bonding that is performed at the chip level. Consequently, it is widely used in the packaging of CPUs, GPUs, and high-speed DRAM chips. Moreover, as bumps can be formed on the entire side of the chip, it is possible to have more inputs and outputs (I/O) than wire bonding — potentially providing higher data-processing speeds. However, flip-chip bonding has its own disadvantages. First, it is difficult to perform multi-chip stacking, which is detrimental for memory products that require high density. In addition, even though flip-chip bonding can connect more I/Os than wire bonding, its bump pitch3 and organic PCB pitch prevent the connection of an even higher number of I/Os. To overcome these limitations, TSV bonding was developed.
Through-silicon via (TSV) bonding
Instead of using the traditional method of wiring to connect chip-to-chip, TSV connects chips vertically by drilling holes in the chip and filling them with conductive materials such as metal to accommodate electrodes. After the wafer with TSV is fabricated, microbumps are formed on its top and bottom sides through packaging before these bumps are connected. As TSV allows the bumps to be connected vertically, it enables multi-chip stacks. Initially, stacks using TSV bonding had four layers before this was increased to eight. More recently, a technique made it possible to stack 12 layers, and in April 2023 SK hynix developed its 12-layer HBM3. While the method for flip-chip bonding with TSV typically uses thermocompression-based non-conductive film (TC-NCF), SK hynix uses the MR-MUF4 process, which can reduce the pressure from stacking and enable self-alignment.5 These features made it possible for SK hynix to develop the world’s first-ever 12-layer HBM3.
4Mass Reflow Molded Underfill (MR-MUF): A process in which semiconductor chips are stacked and a liquid protective material is injected into the space between the chips and then hardened to protect the chips and the surrounding circuitry. Compared to applying a film-type material after each chip is stacked, MR-MUF is a more efficient process and offers effective heat dissipation.
5Self-alignment: The relocation of a die to its proper position through mass reflow during the MR-MUF process. Heat is applied to the chips during this process, causing the relevant bumps to melt and harden in the correct position.
As mentioned above, wire, flip-chip, and TSV bonding serve their respective purposes in the various areas of the packaging process. Nevertheless, there is a new interconnection technique that has recently emerged called copper-to-copper direct bonding, which is a type of hybrid bonding.
Hybrid bonding with chiplets
The term “hybrid” is used to indicate that two types of interfacial bonding6 are being formed simultaneously. The two types of interfacial bonding are: bonding between oxide interfaces and bonding between coppers. This technology is not a new development but has already been used in the mass production of CMOS image sensors for several years. However, it has attracted more attention recently due to the increased use of chiplets. Chiplet technology separates individual chips by function and then reconnects them through packaging to implement a variety of functions on a single chip.
6Interfacial bonding: Bonding in which the surfaces of two bodies in contact with one another are held together by intermolecular forces.
Although the functionality of chiplets is a clear benefit of the technology, the primary reason for their adoption is cost-effectiveness. When all of the functions are implemented on a single chip, the chip size increases and inevitably leads to losses in yield during wafer production. Additionally, while some areas of a chip may require expensive and intricate technology, other areas can be completed with cheaper legacy technology. Thus, the fabrication process becomes expensive as the chip cannot be separated, so fine technology is applied to the whole chip even when only a small area requires it. However, the ability of chiplet technology to separate chip functions enables the use of either advanced or legacy fabrication technologies and, thus, leads to cost savings.
Although the concept of chiplet technology has been around for over a decade, it has not been widely adopted due to the lack of development of packaging technology that can interconnect chips. However, recent advances in chip-to-wafer (C2W) hybrid bonding have significantly accelerated the adoption of chiplet technology. C2W hybrid bonding offers several benefits. First, it allows solder-free bonding that reduces the thickness of the bonding layer, shortens the electrical path, and lowers resistance. Chiplets can, therefore, operate at high speeds without any compromise — just as if it were a single chip. Second, by bonding copper to copper directly, pitches on the bumps can be dramatically reduced. Currently, it is difficult to achieve a bump pitch of 10 micrometers (μm) or less when using solder. However, copper-to-copper direct bonding can reduce the pitch to less than a μm, increasing flexibility in the chip design. Third, it offers advanced thermal dissipation, a feature of packaging that will only continue to grow in importance in the future. Lastly, the thin bonding layer and fine pitch mentioned above affects the form factor of packaging, so the size of the packaging can be dramatically reduced.
However, like the other bonding technologies, hybrid bonding still has to overcome challenges. To ensure robust quality, particle control must be improved at the nanometer scale, and controlling the flatness of the bonding layer remains a major obstacle. Meanwhile, SK hynix plans to use the most high-powered packaging solution to develop hybrid bonding so it can be applied to future HBM products.
Advancing packaging tech with SK hynix’s hybrid bonding
While SK hynix is currently developing hybrid bonding to apply to its upcoming high-density, high-stack HBM product, the company has previously succeeded in stacking eight layers with hybrid bonding for HBM2E in 2022 while completing electrical tests and ensuring basic reliability. This was a significant feat as most cases of hybrid bonding to date have been done through single-layer bonding, or stacking with two chips face-to-face. For HBM2E, SK hynix successfully stacked one base die and eight DRAM dies.
Hybrid bonding is the most talked-about and highlighted bonding technology in the packaging industry. Integrated device manufacturers, foundries, and any company capable of producing advanced packages are concentrating on hybrid bonding. As mentioned above, the technology still has a long way to go regardless of its numerous advantages. Through its leading HBM technology, SK hynix will develop various packaging technologies in addition to hybrid bonding to help packaging technologies and platform solutions reach unprecedented levels.
