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  • QFN: Design – Cleaning – Reliability: What you can’t see can cause failure!

    [vc_row][vc_column][vc_row_inner][vc_column_inner width=”1/2″][vc_video link=”https://vimeo.com/187245910″][vc_column_text disable_pattern=”false” align=”center”]2016-10-13 11.00 FREE Webinar- QFN: Design – Cleaning – Reliability: What you can’t see can cause failure! from Global SMT TV on Vimeo.[/vc_column_text][vc_column_text disable_pattern=”false”]

    Thursday, October 13, 2016

    Reliable electronic hardware is more challenging to reproduce due to component size, residues trapped under bottom terminations, shorter distance between conductors, higher pinout devices in smaller footprint, increased electrical field and environmental factors. Residues under the bottom termination have the highest potential for leakage and are the least understood. Gaining a better understanding of soldering residues, their potential to cause leakage, and test methods for quantifying risk will help reliability engineers understand how clean is clean enough to meet reliability requirements.

    The distance between the land of the bottom of the component and the land on the top of the board surface has a critical impact on the level of contamination, the activity of the residue, the risk for leakage currents and clean-ability under the bottom termination. This webinar will teach circuit board design options for reducing contamination under the bottom termination, testing for the activity of the contamination, cleaning time and force needed to remove the residue.

    Webinar Outline

    • Bottom Terminated Component Cleaning Challenges
    • Ionic Potential of Residues trapped under the Component
    • Design options for Reducing Residue under the Component
    • Cleaning Time and Force needed to Remove the Residue


    Presenter: Dr. Mike Bixenman

    Screen Shot 2016-10-04 at 10.55.04 AM.pngDr. Mike Bixenman is the Chief Technology Officer and Co-Founder of Kyzen Corporation.KYZEN Corporation engineers cleaning materials and processes for cleaning high reliability electronic hardware.

    Mike is an active research fellow studying reliability challenges within high reliability manufacturing segments. He works to gain a deep understanding of these reliability.


    Screen Shot 2016-10-04 at 10.58.03 AM.pngPanelist #1:

    Bruno Tolla is Global Director of R&D for Kester Inc., a leading global supplier of assembly materials for the Electronic Assembly and Semiconductor Packaging industries. He received a Ph.D. in Materials Science from the University of Bordeaux (France), and also holds a Masters in Chemical Engineering from the European School of Chemistry, Polymers and Materials in Strasbourg (France).

    Bruno has 15+ years of experience in the design, development and manufacturing of specialty chemicals and materials for various segments of the electronics industries, including Fuel Cells, Wafer manufacturing, Photovoltaics and Semiconductor Packaging. He holds 8 patents and has authored 11 publications in the fields of Colloidal Science, Materials Chemistry and Electronics Assembly.


    Screen Shot 2016-10-06 at 8.40.04 AM.pngPanelist #2:

    Mark T. McMeen joined STI Electronics Inc. as Vice President of Engineering Services in July of 2000. Prior to joining STI, Mr. McMeen was the Vice President of Engineering and Technical Director of Component Intertechnologies, Inc. He currently oversees the day to day operations of the Engineering Services division of STI which incorporates three entities: Analytical lab, Prototype and Manufacturing Lab and Microelectronics Lab. He has over 25 years of experience in the manufacturing and engineering of printed circuit boards, both flexible and rigid, as well as in the manufacture of electronic assemblies. He has spent most of his career to date in the packaging of components and multi-chip modules and their integration onto printed circuit boards. He currently holds two patents in the fabrication of flexible circuit boards and the processes necessary to imbed integrated circuits inside rigid printed circuit boards.


    Screen Shot 2016-10-04 at 11.02.45 AM.pngPanelist #3:

    Dale Lee is a Senior Staff DFX Strategy Engineer with Plexus Corporation primarily involved with DFX analysis, root cause failure analysis and definition/correlation of design, process and tooling impacts on assembly processes and manufacturing yields.

    Dale has been involved in surface mount design, package & process development and production for over twenty years in various technical and managerial positions. These activities have included research, development and implementation of advanced manufacturing technologies and interconnect techniques, design and development of CSP & BGA packages, PCB & PCBA support, DFM/DFX analysis of flex, rigid-flex & rigid PCB/PCBA’s including supply chain, process qualification and new process introduction for domestic and foreign low, medium and high volume production applications.

    Dale has authored, instructed and presented frequently on topics including advanced SMT packaging, PCB and SMT design, assembly, cleaning, DFM/DFX and rework. He is a past recipient of the Surface Mount Technology Association’s “Excellence in Leadership” award. He has been very involved with multiple industry associations and activities including SMTA, INEMI and IPC.


    [/vc_column_text][/vc_column_inner][vc_column_inner width=”1/2″][vc_raw_js]JTNDc2NyaXB0JTIwdHlwZSUzRCUyMnRleHQlMkZqYXZhc2NyaXB0JTIyJTIwc3JjJTNEJTIyaHR0cHMlM0ElMkYlMkZmb3JtLmpvdGZvcm0uY29tJTJGanNmb3JtJTJGODA1MTU5MjkwOTkxNjUlMjIlM0UlM0MlMkZzY3JpcHQlM0U=[/vc_raw_js][vc_column_text] Sponsored by:
    Screen Shot 2016-09-26 at 2.28.18 PM.png
    Nashville, TN | Penang, Malaysia | Maldegem, Belgium | Manchester, NH | Shanghai, China

    430 Harding Industrial Drive
    Nashville, TN 37211
    +1(615)831-0888 PHONE
    +1(615)831-0889 FAX
    Web: www.kyzen.com

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