Source: EE Times
Chiplets mark a new era of semiconductor innovation, and packaging is an intrinsic part of this ambitious design undertaking. However, while chiplet and packaging technologies work hand in hand to redefine the possibilities of chip integration, this technological tie-up isn’t that simple and straightforward.
In chip packaging, the bare chip die is encapsulated in a supporting case with electrical contacts. The case protects the bare die from physical harm and corrosion and connects the chip to a PCB. This form of chip packaging has existed for decades.
However, due to the slowdown of Moore’s law and the increasing cost of monolithic IC manufacturing, the industry began to adopt advanced packaging techniques like silicon interposers. Advanced packaging also adds to the cost, which only large chips serving high-performance computing (HPC) applications can generally afford.
Then, there’s the added design complexity that comes with advanced packaging solutions. For instance, interposers require an extra piece of silicon, limiting the real estate that designers can put on chips. Moreover, silicon interposers limit overall system-in-package (SiP) size, which lowers wafer test coverage. That, in turn, impacts yield, increases total cost of ownership, and extends production cycle times.
Enter chiplets, which promise smaller SiP footprints at lower power consumption. In other words, compared to advanced packaging technologies, chiplets can achieve similar bandwidth, power efficiency, and latency with die-to-die implementations—all while using standard packaging.
Chiplets split a monolithic IC into multiple functional blocks, reconstitute the functional blocks into separate chiplets, and then re-assemble them at the package level. But chiplets must communicate with each other through dense, fast and high-bandwidth connections. That’s where its tricky relationship with packaging comes to the fore.
Standard or advanced packaging?
Eliyan CEO Ramin Farjadrad says that chiplets eliminate the drawbacks and limitations of advanced packaging. Companies like Eliyan are demonstrating die-to-die implementations in standard organic packaging, which according to Farjadrad, enables the creation of larger SiP solutions, leading to higher performance per power at considerably lower cost and higher yield.
Farjadrad developed the bunch of wires (BoW) chiplet system that was later adopted by the Open Compute Project (OCP) as an interconnect standard. However, now the industry is coalescing around the Universal Chiplet Interconnect Express (UCIe) interface designed to standardize the die-to-die interconnects between chiplets with an open-source design.
The UCIe Consortium is carving the chiplet markets in two broad ranges: standard 2D packaging techniques and more advanced 2.5D techniques, such as chip-on-wafer-on-substrate (CoWoS) and embedded multi-die interconnect bridge (EMIB). Advanced packaging options like CoWoS and EMIB provide higher bandwidth and density.
That’s a testament to packaging’s crucial role in chiplet design and how it affects a chiplet’s performance. Take the case of the UCIe-connected, chiplet-based test chip that Intel recently showcased at its annual event, Innovation 2023. The company fabbed the chip on an Intel 3 process node and paired it with a Synopsys UCIe IP chiplet fabbed on TSMC’s N3E node. The two chiplets interconnect via Intel’s EMIB interface.
Chiplet packaging ecosystem
Not surprisingly, the semiconductor industry is starting to see initiatives at the intersection of packaging and chiplets. First, Faraday Technology has launched a 2.5D/3D packaging service that claims to facilitate seamless integration of multi-source dies in chiplets. The Hsinchu, Taiwan-based, Faraday is working closely with fabs and OSAT suppliers to ensure that it fulfills capacity, yield, quality, reliability and production schedule requirements while providing these services.
Second, Siemens EDA unveiled a design-for-test (DFT) solution for multi-die architectures that connect dies vertically (3D IC) or side-by-side (2.5D) in a single device. The Tessent multi-die software solution can generate die-to-die interconnect patterns and enable package-level tests using Boundary Scan Description Language (BSDL).
According to John Lorenz, senior analyst of computing and software solutions at Yole Intelligence, the economics of adopting a chiplet approach for IC design are tightly linked with the cost and maturity of the interconnect and packaging solution. However, while interface and interconnect technologies are winning the limelight, there’s less clarity on the role of packaging in chiplet designs.
That might change with the advent of the UCIe standard that aims to create a universal interconnect at the package level. Its goal is to facilitate a vibrant, multi-vendor ecosystem for chiplets, so semiconductor firms can simply select chiplets from other designers and snap them into their designs with minimal design and validation work.
In the final analysis, chiplets will cater to both standard organic packaging, as well as advanced packaging solutions. Design engineers will have to determine an optimal package structure for their chiplets in the early stage of the design process alongside die size, substrate, bump pitch and count, power analysis, and thermal simulation.
But one thing is clear: packaging technology is intrinsically tied to the future of chiplet design. And there’s no one-fits-all solution when it comes to packaging in chiplets.